采用Synopsys编译器，编译器和黄金实物的先进芯片设计合成

UNIX is a registered trademark of UNIX Systems Laboratories, Inc.
Verilog is a registered trademark of Cadence Design Systems, Inc.
RSPF and DSPF is a trademark of Cadence Design Systems, Inc.
SDF and SPEF is a trademark of Open Verilog International.
Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! are
registered trademarks of Synopsys, Inc.
Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFT
Compiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler,
Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch,
dont_touch_network and uniquify, are trademarks of Synopsys, Inc.
SolvNET is a service mark of Synopsys, Inc.
All other brand or product names mentioned in this document, are trademarks or
registered trademarks of their respective companies or organizations.
All ideas and concepts provided in this book are authors own, and are not endorsed
by Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in this
book.