资料介绍
T his article describes how to divide clocks by 1.5, 2.5, and by 3, and 5 with a 50% duty-cycle output. Dividing an incoming clock frequency by any integer number is trivial, and division by any even number always generates a 50% duty cycle output. However, sometimes it is necessary to generate a 50% duty cycle frequency that is not an even integer sub-multiple of the source clock. These circuits are useful in XC4000-family and Spartan-family devices, where they are simple and efficient, and both cheaper and faster than any external phase-locked-loop alternative. Virtex devices do not need to use these tricks because they can implement these and many other functions in either of their four dedicated delay-locked-loop circuits, if the incoming clock rate is higher than 25 MHz. How They Work Each circuit assumes a 50/50 duty cycle of the incoming clock, otherwise the fractional divider output will jitter, and the integer divider will have unequal duty cycle. All four circuits use combinatorial feedback around a look-up table, which works perfectly and is glitch-free, but may cause your circuit simulator to fail. These circuits have a look-up table input driven from the clock signal, with minimal skew between the A and B inputs. The chosen vertical clock line must, therefore, also have access to a LUT input. This is best achieved by coding the design as a Hard Macro. Divide by 1.5 in One CLB. This circuit divides the clock by 1.5, generating 60 MHz from a 90 MHz input for example (Figure1)。 The two flip-flops form a ÷3 circuit, and the G and H look-up tables together generate two output periods at the H output. The first output pulse is driven by the A flip-flop, the second output pulse is derived from the B flipflop, but is delayed half an incoming clock cycle. The output stays Low while the clock is High, and stays High, after B has gone Low, until the clock goes Low again. It is this latch circuit that may cause simulator problems. by Peter Alfke, Xilinx Applications Eng
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