A metastability primer

When using a latch or flip-flop in normal circumstances (i.e., when
the device’s setup and hold times are not being violated), the
outputs will respond to a latch enable or clock pulse within some
specified time. These are the propagation delays found in the data
sheets. If, however, the setup and hold times are violated so that the
data input is not a clear one or zero, there is a finite chance that the
flip-flop will not immediately latch a High or Low, but get caught half
way in between. This is the metastable state, and it is manifested in
a bi-stable device by the outputs glitching, going into an undefined
state somewhere between a High and Low, oscillating, or by the
output transition being delayed for an indeterminable time.
Once the flip-flop has entered the metastable state, the probability
that it will still be metastable some time later has been shown to be
an exponentially decreasing function. Because of this property, a
designer can simply wait for some added time after the specified
propagation delay before sampling the flip-flop output so that he can
be assured that the likelihood of metastable failure is remote enough
to be tolerable. On the other hand, one consequence of this is that
there is some probability (albeit vanishingly small) that the device
will remain in a metastable state forever. The designer needs to
know the characteristics of metastability so that he can determine
how long he must wait to achieve his design goals.