AVM Based Unified Verification

This paper addresses the problem of current SoC functional verification productivity
by describing a means of Mentor’s advanced verification methodology (AVM) based
unified verification platform solution.
The continuing growth of system-on-a-chip (SOC) designs has pressured functional
verification engineers to create new and innovative ways of keeping pace.
Increasingly, complex designs, together with traditional functional verification
methods, have resulted in an extraordinary rise in the time required to complete
verification. It has come to a point where traditional methods are no longer a feasible
means of efficiently completing verification tasks. In an effort to close the
productivity gap between design and functional verification, high-level verification
languages have emerged. Such languages employ advanced techniques, such as
constrained randomization, assertion and functional coverage analysis. However, it is
the verification methodology that builds a verification environment that takes full
advantage of these technologies to solve complex verification challenges.