CPU管理与4K SPI EEPROM,X5043, X5045

　　These devices combine four popular functions， Power-on Reset Control， Watchdog Timer， Supply Voltage Supervision， and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost， reduces board space requirements， and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval， the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected， the interval does not change， even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions， resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available， however， Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface （SPI） and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell， providing a minimum endurance of 100，000 cycles and a minimum data retention of 100 years.