32K×8位低功耗CMOS SRAM,AS6C62256A

　　The AS6C62256A is a static RAM manufactured using a CMOS process technology with the following operating modes： - Read - Standby - Write - Data Retention The memory array is based on a 6- transistor cell. The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G， the data inputs， or outputs， are active. In a Read cycle， the data outputs are activated by the falling edge of G， afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change， the data outputs go High-Z until the new information read is available. The data outputs have not preferred state. The Read cycle is finished by the falling edge of W， or by the rising edge of E， respectively. Data retention is guaranteed down to 2 V. With the exception of E， all inputs consist of NOR gates， so that no pull-up/pull-down resistors are required.