抖动器和时钟发生器的6分或13的LVCMOS输出ad9524数据表

　　The AD9524 provides a low power， multi-output， clock distribution function with low jitter performance， along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz. The AD9524 is defined to support the clock requirements for long term evolution （LTE） and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. The input receivers， oscillator， and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO， the device generates six low noise outputs with a range of 1 MHz to 1 GHz， and one dedicated buffered output from the input PLL （PLL1）。 The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to one-half the period of the signal coming out of the VCO. An in-package EEPROM can be programmed through the serial interface to store user defined register settings for power-up and chip reset.