网络时钟发生器两个输出ad9575数据表

　　The AD9575 provides a highly integrated， dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices， Inc.， proven portfolio of high performance， low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector （PFD）， a precision charge pump （CP）， a low phase noise voltage controlled oscillator （VCO）， and pin selectable feedback and output dividers. By connecting an external crystal， popular network output frequencies can be locked to the input reference. The output divider and feedback divider ratios are pin programmable for the required output rates. No external loop filter components are required， thus conserving valuable design time and board space. The AD9575 is available in a 16-lead， 4.4 mm × 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C.