适用于H.264视频解码器的VLD设计

设计了一种适合于H.264 的变字长解码器,根据码流特点进行模块划分,减少硬件开销;采用并行结构解NAL 包,解码效率高采用了桶形移位器进行并行解码每个时钟解一个码字采用Verilog 语言进行设计仿真并通过了FPGA 验证可以在FPGA 上实时解码标准清晰度的H.264 视频用0.18mm CMOS 工艺库作综合.电路规模为1.6 万门左右,最高频率能够达到150MHz.
关键词 专用集成电路 视频解码 变字 长解码 H.264

Abstract This paper proposes an implementation of variable length decoder for H.264. The design is separated into several parts according to the specialty of the code flow so that the hardware cost can be decreased. The NAL packet is decoded by parallel structure module to get the high decoding efficiency. The barrel-shifters which are based on parallel structure can decode one code in every cycle. The module is designed , simulated based on Verilog HDL. The whole design has been verified by FPGA. The FPGA system can decode the standard-definition H.264 video in real-time. The design consists of 16k gates when synthesized based on 0.18mm CMOS library. The highest frequency can reach 150MHz.
Key words ASIC Video decoding Variable length decoding H.264