专注于单片机外围设备：USB音频桥简化嵌入式多媒体设计

　　专注于单片机外围设备：USB音频桥简化嵌入式多媒体设计

　　Now that the humble universal serial bus （USB） has become the de facto interface for virtually every type of consumer gear， there is growing interest in applying its capabilities to audio interfaces. In this article， we will explore a new category of USB bridge devices emerging that can handle many of the details required to support Audio Devices Class applications in hardware. As we will demonstrate， USB’s ample bandwidth， ease of use， and simple control structure make it a natural choice for exchanging and controlling digital high-quality audio streams

　　虽然USB音频很简单，从消费者的角度来看，它不是那么容易的连接器的另一边。这在很大程度上是因为USB协议栈出奇的复杂，能够支持许多不同类型的应用程序，正式地称为USB类。这包括音频设备类，它定义了一个通过USB传输音频的健壮标准化机制。从配送、存储的USB端口提取音频数据，或进一步处理由应用程序的单片机往往需要牢固掌握USB协议层的细节（了解更多关于USB协议本身，看到高新区第”的提示，使用USB嵌入式应用技巧第一部分”）。除了协议本身的复杂性之外，其他与音频相关的问题，如数据流同步和编程编解码器以及数字/模拟转换器（DAC）配置，甚至可以挑战最有经验的嵌入式和音频设计器。

　　To address these issues， devices like Silicon Labs’ CP2114 audio bridge supports the synchronization， stream management， and other tasks that would normally require a significant software development effort. In this article， we will also look at a few ways USB audio bridges provide a novel standard audio configuration interface and methods to synchronize audio data streams in a low-cost， highly integrated single-chip solution.

　　One of the biggest challenges involved with streaming audio over USB is the synchronization of data streams from the host （source） to the device （sink）。 Although USB was originally developed as a simple interface for connecting keyboards， mice and printers， its protocol specification also includes a robust synchronization scheme for “isochronous transfers.” The Audio Device Class definition employs this scheme to transport audio data reliably over the bus. However， the implementation of this mechanism is not a trivial task， and previous implementations have usually been built around relatively powerful embedded systems that included complex data rate converters or expensive phase-locked loops （PLLs） to support the clock accuracy requirements.