关于LPC2930的简介及设计信息

1. General description

The LPC2930 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz， Full-speed USB 2.0 Host/OTG/Device controller， CAN and LIN， 56 kB SRAM， external memory interface， three 10-bit ADCs， and multiple serial and parallel interfaces in a single chip targeted at consumer， industrial， and communication markets. To optimize system power consumption， the LPC2930 has a very flexible Clock Generation Unit （CGU） that provides dynamic clock gating and scaling.

2. Features and benefits

0 ARM968E-S processor running at frequencies of up to 125 MHz maximum.

0 Multilayer AHB system bus at 125 MHz with four separate layers.

0 On-chip memory：

0 Two Tightly Coupled Memories （TCM）， 32 kB Instruction TCM （ITCM）， 32 kB Data TCM （DTCM）。

0 Two separate internal Static RAM （SRAM） instances; 32 kB SRAM and 16 kB SRAM.

0 8 kB ETB SRAM， also usable for code execution and data.

0 Dual-master， eight-channel GPDMA controller on the AHB multilayer matrix which can be used with the SPI interfaces and the UARTs， as well as for memory-to-memory transfers including the TCM memories.

0 External Static Memory Controller （SMC） with eight memory banks; up to 32-bit data bus; up to 24-bit address bus.

0 Serial interfaces：

0 USB 2.0 full-speed Host/OTG/Device controller with dedicated DMA controller and on-chip device PHY.

0 Two-channel CAN controller supporting FullCAN and extensive message filtering

0 Two LIN master controllers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces.

0 Two 550 UARTs with 16-byte Tx and Rx FIFO depths， DMA support， modem control， and RS-485/EIA-485 （9-bit） support.

0 Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep; Tx FIFO and Rx FIFO.

0 Two I2C-bus interfaces.