英特尔80186 80188微处理器内部结构及与80C51,

CONTENTS PAGE
1.0 INTRODUCTION  1
1.1 System Overview  2
1.2 Application Examples  2H
2.0 OVERVIEW OF THE 80186, 80C51,
8052, AND 8044  2
2.1 The 80186 Internal Architecture  2
2.2 The MCS-51 Internal Architecture  3
2.3 The 8044 Internal Architecture  3
3.0 80186/MICROCONTROLLER
INTERACTION  4
4.0 SYSTEM INTERFACE  5
4.1 Command/Status Transfers  5
4.2 Data/Parameter Transfer  5
4.3 Interrupts 6
5.0 COMMAND AND STATUS  7
5.1 Commands  7
5.1.1 Acknowledging Interrupt  7
5.1.2 Operations  7
5.1.3 Illegal Commands  9
5.2 Status 9
5.2.1 Interrupt  9
5.2.2 DMA Operation  9
5.2.3 Error 9
5.2.4 Request to Send  9
5.2.5 Clear to Send  9
5.2.6 Event  9
6.0 HARDWARE DESCRIPTION  10
6.1 Reset 10
6.2 Sending Commands  10
6.3 DMA Transfers  11
6.4 Reading Status  11
CONTENTS PAGEH
7.0 80186/8044 INTERFACE  12
7.1 Configuring the 8044  12
7.2 Transferring a Message with the
8044 13
7.3 Receiving a Message with the
8044 13
7.4 Dumping the 8044 Registers  14
7.5 Aborting an Operation  14
7.6 Disabling Transmission or
Reception  14
7.7 Handling Interrupts  15
CONTENTS PAGE
8.0 8044 IN EXPANDED OPERATION  15
8.1 Transmitting a Message in Expanded
Operation 15
8.2 Receiving a Message in Expanded
Operation 15
9.0 CONCLUSION  15
APPENDIX A: SOFTWARE  A-1