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TABLE OF CONTENTS
Paragraph
Number
Title Page
Number
1.1 Integer Unit User Programming Model . . 1-2
1.1.1 Data Registers (D7 – D0) . . . 1-2
1.1.2 Address Registers (A7 – A0) . 1-2
1.1.3 Program Counter . . . . . 1-3
1.1.4 Condition Code Register . . . . 1-3
1.2 Floating-Point Unit User Programming Model 1-4
1.2.1 Floating-Point Data Registers (FP7 – FP0) . 1-4
1.2.2 Floating-Point Control Register (FPCR) 1-5
1.2.2.1 Exception Enable Byte . . . . 1-5
1.2.2.2 Mode Control Byte . . 1-5
1.2.3 Floating-Point Status Register (FPSR) 1-5
1.2.3.1 Floating-Point Condition Code Byte . 1-5
1.2.3.2 Quotient Byte . . . . . . 1-6
1.2.3.3 Exception Status Byte . . . . . 1-6
1.2.3.4 Accrued Exception Byte . . . 1-7
1.2.4 Floating-Point Instruction Address Register (FPIAR) . 1-8
1.3 Supervisor Programming Model 1-8
1.3.1 Address Register 7 (A7) . . . 1-10
1.3.2 Status Register . . . . . 1-10
1.3.3 Vector Base Register (VBR) 1-11
1.3.4 Alternate Function Code Registers (SFC and DFC) . 1-11
1.3.5 Acu Status Register (MC68EC030 only) . . 1-11
1.3.6 Transparent Translation/access Control Registers . . 1-12
1.3.6.1 Transparent Translation/access Control Register Fields for the
M68030 . . 1-12
1.3.6.2 Transparent Translation/access Control Register Fields for the
M68040 . . 1-13
1.4 Integer Data Formats . . 1-14
1.5 Floating-Point Data Formats . 1-15
1.5.1 Packed Decimal Real Format . . . . . . 1-15
1.5.2 Binary Floating-Point Formats . . . . . . 1-16
1.6 Floating-Point Data Types . . . 1-17
1.6.1 Normalized Numbers . 1-18
1.6.2 Denormalized Numbers . . . . 1-18
1.6.3 Zeros . 1-19
1.6.4 Infinities 1-19
1.6.5 Not-A-Numbers . . . . . 1-19
1.6.6 Data Format and Type Summary . . . 1-20
1.7 Organization of Data in Registers . . . . 1-25
1.7.1 Organization of Integer Data Formats in Registers . . 1-25
1.7.2 Organization of Integer Data Formats in Memory . . . 1-27
1.7.3 Organization of Fpu Data Formats in Registers and Memory . . . . . . 1-30
Section 2
Addressing Capabilities
2.1 Instruction Format . . . . . 2-1
2.2 Effective Addressing Modes . . . 2-4
2.2.1 Data Register Direct Mode . . 2-5
2.2.2 Address Register Direct Mode 2-5
2.2.3 Address Register Indirect Mode . . . . . 2-5
2.2.4 Address Register Indirect with Postincrement Mode. . 2-6
2.2.5 Address Register Indirect with Predecrement Mode . . 2-7
2.2.6 Address Register Indirect with Displacement Mode . . 2-8
2.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode . . . . 2-9
2.2.8 Address Register Indirect with Index (Base Displacement) Mode. . . 2-10
2.2.9 Memory Indirect Postindexed Mode . 2-11
2.2.10 Memory Indirect Preindexed Mode . . 2-12
2.2.11 Program Counter Indirect with Displacement Mode . 2-13
2.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode . . . 2-14
2.2.13 Program Counter Indirect with Index (Base Displacement) Mode. . . 2-15
2.2.14 Program Counter Memory Indirect Postindexed Mode . . . . 2-16
2.2.15 Program Counter Memory Indirect Preindexed Mode 2-17
2.2.16 Absolute Short Addressing Mode . . . 2-18
2.2.17 Absolute Long Addressing Mode . . . . 2-18
2.2.18 Immediate Data . . . . . 2-19
2.3 Effective Addressing Mode Summary . 2-19
2.4 Brief Extension Word Format Compatibility . 2-21
2.5 Full Extension Addressing Modes . . . . 2-22
2.5.1 No Memory Indirect Action Mode . . . 2-24
2.5.2 Memory Indirect Modes . . . . 2-25
2.5.2.1 Memory Indirect with Preindex . . . . 2-25
2.5.2.2 Memory Indirect with Postindex . . . 2-26
2.5.2.3 Memory Indirect with Index Suppressed. 2-27
2.6 Other Data Structures . 2-28
2.6.1 System Stack 2-28
2.6.2 Queues 2-29
Section 3
Instruction Set Summary
3.1 Instruction Summary . . . 3-1
3.1.1 Data Movement Instructions . 3-5
3.1.2 Integer Arithmetic Instructions 3-6
3.1.3 Logical Instructions . . . 3-8
3.1.4 Shift and Rotate Instructions . 3-8
3.1.5 Bit Manipulation Instructions 3-10
3.1.6 Bit Field Instructions . 3-10
3.1.7 Binary-Coded Decimal Instructions . . 3-11
3.1.8 Program Control Instructions 3-11
3.1.9 System Control Instructions . 3-12
3.1.10 Cache Control Instructions (MC68040) 3-14
3.1.11 Multiprocessor Instructions . 3-14
3.1.12 Memory Management Unit (MMU) Instructions. . . . . 3-15
3.1.13 Floating-Point Arithmetic Instructions 3-15
3.2 Integer Unit Condition Code Computation . . 3-17
3.3 Instruction Examples . . 3-20
3.3.1 Using the Cas and Cas2 Instructions 3-20
3.3.2 Using the Moves Instruction 3-20
3.3.3 Nested Subroutine Calls . . . 3-20
3.3.4 Bit Field Instructions . 3-20
3.3.5 Pipeline Synchronization with the Nop Instruction. . . 3-21
3.4 Floating-Point Instruction Details . . . . . 3-21
3.5 Floating-Point Computational Accuracy 3-23
3.5.1 Intermediate Result . . 3-24
3.5.2 Rounding the Result . 3-25
3.6 Floating-Point Postprocessing 3-27
3.6.1 Underflow, Round, Overflow 3-28
3.6.2 Conditional Testing . . 3-28
3.7 Instruction Descriptions 3-32
8.1 Instruction Format 8-1
8.1.1 Coprocessor ID Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 Effective Address Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.3 Register/Memory Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.4 Source Specifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.5 Destination Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.6 Conditional Predicate Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7.1 Count Register Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7.2 Register Field . 8-2
8.1.8 Size Field . . . . . . 8-4
8.1.9 Opmode Field . . 8-4
8.1.10 Address/Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2 Operation Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Appendix A
Processor Instruction Summary
A.1 MC68000, MC68008, MC68010 Processors . . . . . . . . . . . . . . . . . . . . A-12
A.1.1 M68000, MC68008, and MC68010 Instruction Set . . . . . . . . . . . . . . A-12
A.1.2 MC68000, MC68008, and MC68010 Addressing Modes . . . . . . . . . A-16
A.2 MC68020 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.2.1 MC68020 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.2.2 MC68020 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.3 MC68030 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.3.1 MC68030 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.3.2 MC68030 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
A.4 MC68040 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.4.1 MC68040 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.4.2 MC68040 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-29
A.5 MC68881/MC68882 Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30
A.5.1 MC68881/MC68882 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . A-30
A.5.2 MC68881/MC68882 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . A-31
A.6 MC68851 Coprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
A.6.1 MC68851 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
A.6.2 MC68851 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
Appendix B
Exception Processing Reference
B.1 Exception Vector Assignments for the M68000 Family . . . . . . . . . . . . . B-1
B.2 Exception Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
B.3 Floating-Point Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Paragraph
Number
Title Page
Number
Appendix C
S-Record Output Format
C.1 S-Record Content . C-1
C.2 S-Record Types . . C-2
C.3 S-Record Creation C-3
LIST OF FIGURES
Figure
Number
Title Page
Number
1-1 M68000 Family User Programming Model 1-2
1-2 M68000 Family Floating-Point Unit User Programming Model... 1-4
1-3 Floating-Point Control Register ......... 1-5
1-4 FPSR Condition Code Byte. 1-6
1-5 FPSR Quotient Code Byte 1-6
1-6 FPSR Exception Status Byte ............ 1-6
1-7 FPSR Accrued Exception Byte ......... 1-7
1-8 Status Register.. 1-11
1-9 MC68030 Transparent Translation/MC68EC030 Access
Control Register Format.. 1-12
1-10 MC68040 and MC68LC040 Transparent Translation/MC68EC040
Access Control Register Format ..... 1-13
1-11 Packed Decimal Real Format ......... 1-16
1-12 Binary Floating-Point Data Formats 1-16
1-13 Normalized Number Format............ 1-18
1-14 Denormalized Number Format........ 1-18
1-15 Zero Format ...... 1-19
1-16 Infinity Format ... 1-19
1-17 Not-A-Number Format..... 1-19
1-19 Organization of Integer Data Formats in Address Registers..... 1-26
1-18 Organization of Integer Data Formats in Data Registers .......... 1-26
1-20 Memory Operand Addressing ......... 1-27
1-21 Memory Organization for Integer Operands......... 1-29
1-22 Organization of FPU Data Formats in Memory.... 1-30
2-1 Instruction Word General Format...... 2-1
2-2 Instruction Word Specification Formats ... 2-2
2-3 M68000 Family Brief Extension Word Formats.... 2-21
2-4 Addressing Array Items... 2-23
2-5 No Memory Indirect Action 2-24
2-6 Memory Indirect with Preindex........ 2-26
2-7 Memory Indirect with Postindex ..... 2-27
2-8 Memory Indirect with Index Suppress... 2-27
3-1 Intermediate Result Format 3-24
3-2 Rounding Algorithm Flowchart........ 3-26
3-3 Instruction Description Format ........ 3-33
B-1 MC68000 Group 1 and 2 Exception Stack Frame .B-3
B-2 MC68000 Bus or Address Error Exception Stack Frame............B-3
B-3 Four-Word Stack Frame, Format $0 .B-3
B-4 Throwaway Four-Word Stack Frame, Format $1...B-3
LIST OF FIGURES (Concluded)
B-5 Six-Word Stack Frame, Format $2....B-4
B-6 MC68040 Floating-Point Post-Instruction Stack Frame, Format $3...B-4
B-7 MC68EC040 and MC68LC040 Floating-Point Unimplemented
Stack Frame, Format $4 ...B-5
B-8 MC68040 Access Error Stack Frame, Format $7 .B-5
B-9 MC68010 Bus and Address Error Stack Frame, Format $8 ......B-6
B-10 MC68020 Bus and MC68030 Coprocessor Mid-Instruction
Stack Frame, Format $9 ...B-6
B-11 MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A.B-7
B-12 MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B.B-8
B-13 CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C.....B-8
B-14 CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C ...B-9
B-15 CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C......B-9
B-16 MC68881/MC68882 and MC68040 Null Stack FrameB-10
B-17 MC68881 Idle Stack Frame ...........B-10
B-18 MC68881 Busy Stack Frame .........B-11
B-19 MC68882 Idle Stack Frame ............B-11
B-20 MC68882 Busy Stack Frame ..........B-11
B-21 MC68040 Idle Busy Stack Frame ...B-12
B-22 MC68040 Unimplimented Instruction Stack Frame.....B-12
B-23 MC68040 Busy Stack Frame ..........B-13
C-1 Five Fields of an S-RecordC-1
C-2 Transmission of an S1 Record..........C-4
LIST OF TABLES
Table
Number
Title Page
Number
1-1 Supervisor Registers Not Related To Paged Memory Management 1-9
1-2 Supervisor Registers Related To Paged Memory Management..... 1-10
1-3 Integer Data Formats ..... 1-15
1-4 Single-Precision Real Format Summary Data Format 1-21
1-5 Double-Precision Real Format Summary............ 1-22
1-6 Extended-Precision Real Format Summary........ 1-23
1-6 Extended-Precision Real Format Summary (Continued)......... 1-24
1-7 Packed Decimal Real Format Summary 1-24
1-8 MC68040 FPU Data Formats and Data Types ... 1-30
2-1 Instruction Word Format Field Definitions 2-3
2-2 IS-I/IS Memory Indirect Action Encodings 2-4
2-3 Immediate Operand Location......... 2-19
2-4 Effective Addressing Modes and Categories ...... 2-20
3-1 Notational Conventions .... 3-2
3-1 Notational Conventions (Continued) 3-3
3-1 Notational Conventions (Concluded) . 3-4
3-2 Data Movement Operation Format... 3-6
3-3 Integer Arithmetic Operation Format 3-7
3-4 Logical Operation Format. 3-8
3-5 Shift and Rotate Operation Format .. 3-9
3-6 Bit Manipulation Operation Format 3-10
3-7 Bit Field Operation Format 3-10
3-8 Binary-Coded Decimal Operation Format........... 3-11
3-9 Program Control Operation Format 3-12
3-10 System Control Operation Format . 3-13
3-11 Cache Control Operation Format... 3-14
3-12 Multiprocessor Operations 3-14
3-13 MMU Operation Format . 3-15
3-14 Dyadic Floating-Point Operation Format 3-16
3-15 Dyadic Floating-Point Operations .. 3-16
3-16 Monadic Floating-Point Operation Format .......... 3-16
3-17 Monadic Floating-Point Operations 3-17
3-18 Integer Unit Condition Code Computations......... 3-18
3-19 Conditional Tests ........... 3-19
3-20 Operation Table Example (FADD Instruction)..... 3-22
3-21 FPCR Encodings............ 3-25
3-22 FPCC Encodings............ 3-29
3-23 Floating-Point Conditional Tests .... 3-31
5-1 Directly Supported Floating-Point Instructions ...... 5-2
5-2 Indirectly Supported Floating-Point Instructions.... 5-3
LIST OF TABLES (Continued)
7-1 MC68020 Instructions Not Supported 7-1
7-2 M68000 Family Addressing Modes.. 7-2
7-3 CPU32 Instruction Set...... 7-3
8-1 Conditional Predicate Field Encoding 8-3
8-2 Operation Code Map........ 8-4
A-1 M68000 Family Instruction Set And Processor Cross-Reference.....A-1
A-2 M68000 Family Instruction Set.........A-8
A-3 MC68000 and MC68008 Instruction SetA-12
A-4 MC68010 Instruction SetA-14
A-5 MC68000, MC68008, and MC68010 Data Addressing ModesA-16
A-6 MC68020 Instruction Set Summary .A-17
A-7 MC68020 Data Addressing Modes A-20
A-8 MC68030 Instruction Set Summary .A-21
A-9 MC68030 Data Addressing Modes A-24
A-10 MC68040 Instruction SetA-25
A-11 MC68040 Data Addressing Modes A-29
A-12 MC68881/MC68882 Instruction Set.A-30
A-13 MC68851 Instruction SetA-31
B-1 Exception Vector Assignments for the M68000 FamilyB-2
C-1 Field Composition of an S-Record ...C-1
C-2 ASCII Code .C-5
Paragraph
Number
Title Page
Number
1.1 Integer Unit User Programming Model . . 1-2
1.1.1 Data Registers (D7 – D0) . . . 1-2
1.1.2 Address Registers (A7 – A0) . 1-2
1.1.3 Program Counter . . . . . 1-3
1.1.4 Condition Code Register . . . . 1-3
1.2 Floating-Point Unit User Programming Model 1-4
1.2.1 Floating-Point Data Registers (FP7 – FP0) . 1-4
1.2.2 Floating-Point Control Register (FPCR) 1-5
1.2.2.1 Exception Enable Byte . . . . 1-5
1.2.2.2 Mode Control Byte . . 1-5
1.2.3 Floating-Point Status Register (FPSR) 1-5
1.2.3.1 Floating-Point Condition Code Byte . 1-5
1.2.3.2 Quotient Byte . . . . . . 1-6
1.2.3.3 Exception Status Byte . . . . . 1-6
1.2.3.4 Accrued Exception Byte . . . 1-7
1.2.4 Floating-Point Instruction Address Register (FPIAR) . 1-8
1.3 Supervisor Programming Model 1-8
1.3.1 Address Register 7 (A7) . . . 1-10
1.3.2 Status Register . . . . . 1-10
1.3.3 Vector Base Register (VBR) 1-11
1.3.4 Alternate Function Code Registers (SFC and DFC) . 1-11
1.3.5 Acu Status Register (MC68EC030 only) . . 1-11
1.3.6 Transparent Translation/access Control Registers . . 1-12
1.3.6.1 Transparent Translation/access Control Register Fields for the
M68030 . . 1-12
1.3.6.2 Transparent Translation/access Control Register Fields for the
M68040 . . 1-13
1.4 Integer Data Formats . . 1-14
1.5 Floating-Point Data Formats . 1-15
1.5.1 Packed Decimal Real Format . . . . . . 1-15
1.5.2 Binary Floating-Point Formats . . . . . . 1-16
1.6 Floating-Point Data Types . . . 1-17
1.6.1 Normalized Numbers . 1-18
1.6.2 Denormalized Numbers . . . . 1-18
1.6.3 Zeros . 1-19
1.6.4 Infinities 1-19
1.6.5 Not-A-Numbers . . . . . 1-19
1.6.6 Data Format and Type Summary . . . 1-20
1.7 Organization of Data in Registers . . . . 1-25
1.7.1 Organization of Integer Data Formats in Registers . . 1-25
1.7.2 Organization of Integer Data Formats in Memory . . . 1-27
1.7.3 Organization of Fpu Data Formats in Registers and Memory . . . . . . 1-30
Section 2
Addressing Capabilities
2.1 Instruction Format . . . . . 2-1
2.2 Effective Addressing Modes . . . 2-4
2.2.1 Data Register Direct Mode . . 2-5
2.2.2 Address Register Direct Mode 2-5
2.2.3 Address Register Indirect Mode . . . . . 2-5
2.2.4 Address Register Indirect with Postincrement Mode. . 2-6
2.2.5 Address Register Indirect with Predecrement Mode . . 2-7
2.2.6 Address Register Indirect with Displacement Mode . . 2-8
2.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode . . . . 2-9
2.2.8 Address Register Indirect with Index (Base Displacement) Mode. . . 2-10
2.2.9 Memory Indirect Postindexed Mode . 2-11
2.2.10 Memory Indirect Preindexed Mode . . 2-12
2.2.11 Program Counter Indirect with Displacement Mode . 2-13
2.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode . . . 2-14
2.2.13 Program Counter Indirect with Index (Base Displacement) Mode. . . 2-15
2.2.14 Program Counter Memory Indirect Postindexed Mode . . . . 2-16
2.2.15 Program Counter Memory Indirect Preindexed Mode 2-17
2.2.16 Absolute Short Addressing Mode . . . 2-18
2.2.17 Absolute Long Addressing Mode . . . . 2-18
2.2.18 Immediate Data . . . . . 2-19
2.3 Effective Addressing Mode Summary . 2-19
2.4 Brief Extension Word Format Compatibility . 2-21
2.5 Full Extension Addressing Modes . . . . 2-22
2.5.1 No Memory Indirect Action Mode . . . 2-24
2.5.2 Memory Indirect Modes . . . . 2-25
2.5.2.1 Memory Indirect with Preindex . . . . 2-25
2.5.2.2 Memory Indirect with Postindex . . . 2-26
2.5.2.3 Memory Indirect with Index Suppressed. 2-27
2.6 Other Data Structures . 2-28
2.6.1 System Stack 2-28
2.6.2 Queues 2-29
Section 3
Instruction Set Summary
3.1 Instruction Summary . . . 3-1
3.1.1 Data Movement Instructions . 3-5
3.1.2 Integer Arithmetic Instructions 3-6
3.1.3 Logical Instructions . . . 3-8
3.1.4 Shift and Rotate Instructions . 3-8
3.1.5 Bit Manipulation Instructions 3-10
3.1.6 Bit Field Instructions . 3-10
3.1.7 Binary-Coded Decimal Instructions . . 3-11
3.1.8 Program Control Instructions 3-11
3.1.9 System Control Instructions . 3-12
3.1.10 Cache Control Instructions (MC68040) 3-14
3.1.11 Multiprocessor Instructions . 3-14
3.1.12 Memory Management Unit (MMU) Instructions. . . . . 3-15
3.1.13 Floating-Point Arithmetic Instructions 3-15
3.2 Integer Unit Condition Code Computation . . 3-17
3.3 Instruction Examples . . 3-20
3.3.1 Using the Cas and Cas2 Instructions 3-20
3.3.2 Using the Moves Instruction 3-20
3.3.3 Nested Subroutine Calls . . . 3-20
3.3.4 Bit Field Instructions . 3-20
3.3.5 Pipeline Synchronization with the Nop Instruction. . . 3-21
3.4 Floating-Point Instruction Details . . . . . 3-21
3.5 Floating-Point Computational Accuracy 3-23
3.5.1 Intermediate Result . . 3-24
3.5.2 Rounding the Result . 3-25
3.6 Floating-Point Postprocessing 3-27
3.6.1 Underflow, Round, Overflow 3-28
3.6.2 Conditional Testing . . 3-28
3.7 Instruction Descriptions 3-32
8.1 Instruction Format 8-1
8.1.1 Coprocessor ID Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 Effective Address Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.3 Register/Memory Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.4 Source Specifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.5 Destination Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.6 Conditional Predicate Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7.1 Count Register Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.7.2 Register Field . 8-2
8.1.8 Size Field . . . . . . 8-4
8.1.9 Opmode Field . . 8-4
8.1.10 Address/Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2 Operation Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Appendix A
Processor Instruction Summary
A.1 MC68000, MC68008, MC68010 Processors . . . . . . . . . . . . . . . . . . . . A-12
A.1.1 M68000, MC68008, and MC68010 Instruction Set . . . . . . . . . . . . . . A-12
A.1.2 MC68000, MC68008, and MC68010 Addressing Modes . . . . . . . . . A-16
A.2 MC68020 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.2.1 MC68020 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.2.2 MC68020 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.3 MC68030 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.3.1 MC68030 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.3.2 MC68030 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
A.4 MC68040 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.4.1 MC68040 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.4.2 MC68040 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-29
A.5 MC68881/MC68882 Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30
A.5.1 MC68881/MC68882 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . A-30
A.5.2 MC68881/MC68882 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . A-31
A.6 MC68851 Coprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
A.6.1 MC68851 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
A.6.2 MC68851 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
Appendix B
Exception Processing Reference
B.1 Exception Vector Assignments for the M68000 Family . . . . . . . . . . . . . B-1
B.2 Exception Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
B.3 Floating-Point Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Paragraph
Number
Title Page
Number
Appendix C
S-Record Output Format
C.1 S-Record Content . C-1
C.2 S-Record Types . . C-2
C.3 S-Record Creation C-3
LIST OF FIGURES
Figure
Number
Title Page
Number
1-1 M68000 Family User Programming Model 1-2
1-2 M68000 Family Floating-Point Unit User Programming Model... 1-4
1-3 Floating-Point Control Register ......... 1-5
1-4 FPSR Condition Code Byte. 1-6
1-5 FPSR Quotient Code Byte 1-6
1-6 FPSR Exception Status Byte ............ 1-6
1-7 FPSR Accrued Exception Byte ......... 1-7
1-8 Status Register.. 1-11
1-9 MC68030 Transparent Translation/MC68EC030 Access
Control Register Format.. 1-12
1-10 MC68040 and MC68LC040 Transparent Translation/MC68EC040
Access Control Register Format ..... 1-13
1-11 Packed Decimal Real Format ......... 1-16
1-12 Binary Floating-Point Data Formats 1-16
1-13 Normalized Number Format............ 1-18
1-14 Denormalized Number Format........ 1-18
1-15 Zero Format ...... 1-19
1-16 Infinity Format ... 1-19
1-17 Not-A-Number Format..... 1-19
1-19 Organization of Integer Data Formats in Address Registers..... 1-26
1-18 Organization of Integer Data Formats in Data Registers .......... 1-26
1-20 Memory Operand Addressing ......... 1-27
1-21 Memory Organization for Integer Operands......... 1-29
1-22 Organization of FPU Data Formats in Memory.... 1-30
2-1 Instruction Word General Format...... 2-1
2-2 Instruction Word Specification Formats ... 2-2
2-3 M68000 Family Brief Extension Word Formats.... 2-21
2-4 Addressing Array Items... 2-23
2-5 No Memory Indirect Action 2-24
2-6 Memory Indirect with Preindex........ 2-26
2-7 Memory Indirect with Postindex ..... 2-27
2-8 Memory Indirect with Index Suppress... 2-27
3-1 Intermediate Result Format 3-24
3-2 Rounding Algorithm Flowchart........ 3-26
3-3 Instruction Description Format ........ 3-33
B-1 MC68000 Group 1 and 2 Exception Stack Frame .B-3
B-2 MC68000 Bus or Address Error Exception Stack Frame............B-3
B-3 Four-Word Stack Frame, Format $0 .B-3
B-4 Throwaway Four-Word Stack Frame, Format $1...B-3
LIST OF FIGURES (Concluded)
B-5 Six-Word Stack Frame, Format $2....B-4
B-6 MC68040 Floating-Point Post-Instruction Stack Frame, Format $3...B-4
B-7 MC68EC040 and MC68LC040 Floating-Point Unimplemented
Stack Frame, Format $4 ...B-5
B-8 MC68040 Access Error Stack Frame, Format $7 .B-5
B-9 MC68010 Bus and Address Error Stack Frame, Format $8 ......B-6
B-10 MC68020 Bus and MC68030 Coprocessor Mid-Instruction
Stack Frame, Format $9 ...B-6
B-11 MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A.B-7
B-12 MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B.B-8
B-13 CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C.....B-8
B-14 CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C ...B-9
B-15 CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C......B-9
B-16 MC68881/MC68882 and MC68040 Null Stack FrameB-10
B-17 MC68881 Idle Stack Frame ...........B-10
B-18 MC68881 Busy Stack Frame .........B-11
B-19 MC68882 Idle Stack Frame ............B-11
B-20 MC68882 Busy Stack Frame ..........B-11
B-21 MC68040 Idle Busy Stack Frame ...B-12
B-22 MC68040 Unimplimented Instruction Stack Frame.....B-12
B-23 MC68040 Busy Stack Frame ..........B-13
C-1 Five Fields of an S-RecordC-1
C-2 Transmission of an S1 Record..........C-4
LIST OF TABLES
Table
Number
Title Page
Number
1-1 Supervisor Registers Not Related To Paged Memory Management 1-9
1-2 Supervisor Registers Related To Paged Memory Management..... 1-10
1-3 Integer Data Formats ..... 1-15
1-4 Single-Precision Real Format Summary Data Format 1-21
1-5 Double-Precision Real Format Summary............ 1-22
1-6 Extended-Precision Real Format Summary........ 1-23
1-6 Extended-Precision Real Format Summary (Continued)......... 1-24
1-7 Packed Decimal Real Format Summary 1-24
1-8 MC68040 FPU Data Formats and Data Types ... 1-30
2-1 Instruction Word Format Field Definitions 2-3
2-2 IS-I/IS Memory Indirect Action Encodings 2-4
2-3 Immediate Operand Location......... 2-19
2-4 Effective Addressing Modes and Categories ...... 2-20
3-1 Notational Conventions .... 3-2
3-1 Notational Conventions (Continued) 3-3
3-1 Notational Conventions (Concluded) . 3-4
3-2 Data Movement Operation Format... 3-6
3-3 Integer Arithmetic Operation Format 3-7
3-4 Logical Operation Format. 3-8
3-5 Shift and Rotate Operation Format .. 3-9
3-6 Bit Manipulation Operation Format 3-10
3-7 Bit Field Operation Format 3-10
3-8 Binary-Coded Decimal Operation Format........... 3-11
3-9 Program Control Operation Format 3-12
3-10 System Control Operation Format . 3-13
3-11 Cache Control Operation Format... 3-14
3-12 Multiprocessor Operations 3-14
3-13 MMU Operation Format . 3-15
3-14 Dyadic Floating-Point Operation Format 3-16
3-15 Dyadic Floating-Point Operations .. 3-16
3-16 Monadic Floating-Point Operation Format .......... 3-16
3-17 Monadic Floating-Point Operations 3-17
3-18 Integer Unit Condition Code Computations......... 3-18
3-19 Conditional Tests ........... 3-19
3-20 Operation Table Example (FADD Instruction)..... 3-22
3-21 FPCR Encodings............ 3-25
3-22 FPCC Encodings............ 3-29
3-23 Floating-Point Conditional Tests .... 3-31
5-1 Directly Supported Floating-Point Instructions ...... 5-2
5-2 Indirectly Supported Floating-Point Instructions.... 5-3
LIST OF TABLES (Continued)
7-1 MC68020 Instructions Not Supported 7-1
7-2 M68000 Family Addressing Modes.. 7-2
7-3 CPU32 Instruction Set...... 7-3
8-1 Conditional Predicate Field Encoding 8-3
8-2 Operation Code Map........ 8-4
A-1 M68000 Family Instruction Set And Processor Cross-Reference.....A-1
A-2 M68000 Family Instruction Set.........A-8
A-3 MC68000 and MC68008 Instruction SetA-12
A-4 MC68010 Instruction SetA-14
A-5 MC68000, MC68008, and MC68010 Data Addressing ModesA-16
A-6 MC68020 Instruction Set Summary .A-17
A-7 MC68020 Data Addressing Modes A-20
A-8 MC68030 Instruction Set Summary .A-21
A-9 MC68030 Data Addressing Modes A-24
A-10 MC68040 Instruction SetA-25
A-11 MC68040 Data Addressing Modes A-29
A-12 MC68881/MC68882 Instruction Set.A-30
A-13 MC68851 Instruction SetA-31
B-1 Exception Vector Assignments for the M68000 FamilyB-2
C-1 Field Composition of an S-Record ...C-1
C-2 ASCII Code .C-5
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