8XC251SB嵌入式微控制器用户手册

CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS.... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY .... 1-3
1.3 RELATED DOCUMENTS . 1-5
1.3.1 Data Sheet ....1-6
1.3.2 Application Notes .......1-6
1.4 CUSTOMER SERVICE... 1-7
1.4.1 How to Use Intel's FaxBack Service .1-7
1.4.2 How to Use Intel's Application BBS ..1-8
1.4.3 How to Find the Latest ApBUILDER Files and Hypertext Manuals and
Data Sheets on the BBS ......1-9
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 8XC251SB CORE... 2-4
2.1.1 CPU ....2-4
2.1.2 Clock and Reset Unit .2-5
2.1.3 Interrupt Handler 2-6
2.1.4 On-chip Code Memory .2-6
2.1.5 On-chip RAM 2-7
2.2 ON-CHIP PERIPHERALS. 2-7
2.2.1 Timer/Counters and Watchdog Timer ....2-7
2.2.2 Programmable Counter Array (PCA) 2-7
2.2.3 Serial I/O Port ....2-8
CHAPTER 3
ADDRESS SPACES
3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS . 3-1
3.1.1 Compatibility with the MCS® 51 Architecture .3-2
3.2 THE 8XC251SB MEMORY SPACE....... 3-5
3.2.1 On-chip General-purpose Data RAM 3-6
3.2.2 On-chip Code Memory (87C251SB/83C251SB) ......3-6
3.2.2.1 Accessing On-chip Code Memory in Region 00: .3-6
3.2.3 External Memory 3-8
3.3 THE 8XC251SB REGISTER FILE. 3-8
3.3.1 Byte, Word, and Dword Registers .....3-8
3.3.2 Dedicated Registers .3-10
CONTENTS
iv
3.3.2.1 Accumulator and B Register ..3-10
3.3.2.2 Extended Data Pointer, DPX .3-10
3.3.2.3 Extended Stack Pointer, SPX 3-11
3.4 SPECIAL FUNCTION REGISTERS (SFRS) .... 3-12
CHAPTER 4
PROGRAMMING
4.1 BINARY MODE AND SOURCE MODE CONFIGURATIONS ... 4-1
4.1.1 Selecting Binary Mode or Source Mode .4-2
4.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE .... 4-4
4.2.1 Data Types ....4-4
4.2.2 Register Notation .......4-4
4.2.3 Address Notation .......4-5
4.2.4 Addressing Modes .....4-5
4.3 DATA INSTRUCTIONS .. 4-6
4.3.1 Data Addressing Modes .......4-6
4.3.1.1 Register Addressing ...4-8
4.3.1.2 Immediate .4-8
4.3.1.3 Direct ...4-8
4.3.1.4 Indirect .4-9
4.3.1.5 Displacement ....4-9
4.3.2 Arithmetic Instructions 4-10
4.3.3 Logical Instructions ..4-11
4.3.4 Data Transfer Instructions ..4-11
4.4 BIT INSTRUCTIONS .... 4-12
4.4.1 Bit Addressing ..4-12
4.5 CONTROL INSTRUCTIONS .. 4-14
4.5.1 Addressing Modes for Control Instructions ..4-14
4.5.2 Conditional Jumps ...4-15
4.5.3 Unconditional Jumps 4-16
4.5.4 Calls and Returns ....4-16
4.6 PROGRAM STATUS WORDS .... 4-17
CHAPTER 5
INTERRUPT SYSTEM
5.1 OVERVIEW ....... 5-1
5.2 8XC251SB INTERRUPT SOURCES..... 5-3
5.2.1 External Interrupts ......5-3
5.2.2 Timer Interrupts ..5-4
5.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT.... 5-5
5.4 SERIAL PORT INTERRUPT..... 5-5
5.5 INTERRUPT ENABLE .... 5-5
5.6 INTERRUPT PRIORITIES 5-6
5.7 INTERRUPT PROCESSING .... 5-9
5.7.1 Minimum Fixed Interrupt Time 5-10
5.7.2 Variable Interrupt Parameters .5-10
5.7.2.1 Response Time Variables .....5-10
5.7.2.2 Computation of Worst-case Latency With Variables .5-12
5.7.2.3 Latency Calculations 5-13
5.7.2.4 Blocking Conditions ..5-14
5.7.2.5 Interrupt Vector Cycle ....5-14
5.7.3 ISRs in Process .......5-15
CHAPTER 6
INPUT/OUTPUT PORTS
6.1 INPUT/OUTPUT PORT OVERVIEW..... 6-1
6.2 I/O CONFIGURATIONS.. 6-2
6.3 PORT 1 AND PORT 3 .... 6-2
6.4 PORT 0 AND PORT 2 .... 6-2
6.5 READ-MODIFY-WRITE INSTRUCTIONS.. 6-5
6.6 QUASI-BIDIRECTIONAL PORT OPERATION... 6-5
6.7 PORT LOADING 6-7
6.8 EXTERNAL MEMORY ACCESS... 6-7
CHAPTER 7
TIMER/COUNTERS AND WATCHDOG TIMER
7.1 TIMER/COUNTER OVERVIEW 7-1
7.2 TIMER/COUNTER OPERATION... 7-1
7.3 TIMER 0... 7-4
7.3.1 Mode 0 (13-bit Timer) 7-4
7.3.2 Mode 1 (16-bit Timer) 7-5
7.3.3 Mode 2 (8-bit Timer With Auto-reload) ...7-5
7.3.4 Mode 3 (Two 8-bit Timers) ...7-5
7.4 TIMER 1... 7-6
7.4.1 Mode 0 (13-bit Timer) 7-9
7.4.2 Mode 1 (16-bit Timer) 7-9
7.4.3 Mode 2 (8-bit Timer with Auto-reload) ....7-9
7.4.4 Mode 3 (Halt) 7-9
7.5 TIMER 0/1 APPLICATIONS...... 7-9
7.5.1 Auto-load Setup Example ....7-9
7.5.2 Pulse Width Measurements ....7-10
7.6 TIMER 2. 7-10
7.6.1 Capture Mode ..7-11
7.6.2 Auto-reload Mode ....7-12
7.6.2.1 Up Counter Operation ...7-12
7.6.2.2 Up/Down Counter Operation .7-13
7.6.3 Baud Rate Generator Mode ....7-14
7.6.4 Clock-out Mode 7-14
7.7 WATCHDOG TIMER .... 7-16
7.7.1 Description ..7-16
7.7.2 Using the WDT .7-18
7.7.3 WDT During Idle Mode ......7-18
7.7.4 WDT During PowerDown ...7-18
CHAPTER 8
PROGRAMMABLE COUNTER ARRAY
8.1 PCA DESCRIPTION....... 8-1
8.2 PCA TIMER/COUNTER.. 8-2
8.3 PCA COMPARE/CAPTURE MODULES .... 8-5
8.3.1 16-bit Capture Mode ..8-5
8.3.2 Compare Modes 8-7
8.3.3 16-bit Software Timer Mode .8-7
8.3.4 High-speed Output Mode .....8-8
8.3.5 PCA Watchdog Timer Mode 8-9
8.3.6 Pulse Width Modulation Mode 8-11
CHAPTER 9
SERIAL I/O PORT
9.1 OVERVIEW ....... 9-1
9.2 MODES OF OPERATION. 9-4
9.2.1 Synchronous Mode (Mode 0) ....9-4
9.2.1.1 Transmission (Mode 0) ....9-4
9.2.1.2 Reception (Mode 0) ....9-5
9.2.2 Asynchronous Modes (Modes 1, 2, and 3) ....9-6
9.2.2.1 Transmission (Modes 1, 2, 3) ..9-6
9.2.2.2 Reception (Modes 1, 2, 3) .......9-6
9.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3).... 9-7
9.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3) .. 9-7
9.5 AUTOMATIC ADDRESS RECOGNITION.. 9-7
9.5.1 Given Address ...9-8
9.5.2 Broadcast Address .....9-9
9.5.3 Reset Addresses ......9-10
9.6 BAUD RATES.. 9-10
9.6.1 Baud Rate for Mode 0 9-10
9.6.2 Baud Rates for Mode 2 ......9-10
9.6.3 Baud Rates for Modes 1 and 3 .......9-10
9.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) .....9-11
9.6.3.2 Selecting Timer 1 as the Baud Rate Generator 9-11
9.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) .....9-12
9.6.3.4 Selecting Timer 2 as the Baud Rate Generator 9-12
CHAPTER 10
MINIMUM HARDWARE SETUP
10.1 MINIMUM HARDWARE SETUP.. 10-1
10.2 ELECTRICAL ENVIRONMENT... 10-2
10.2.1 Power and Ground Pins .....10-2
10.2.2 Unused Pins 10-2
10.2.3 Noise Considerations .10-2
10.3 CLOCK SOURCES....... 10-3
10.3.1 On-chip Oscillator (Crystal) 10-3
10.3.2 On-chip Oscillator (Ceramic Resonator) ......10-4
10.3.3 External Clock ..10-4
10.4 RESET... 10-5
10.4.1 Externally Initiated Resets .10-6
10.4.2 WDT Initiated Resets .10-6
10.4.3 Reset Operation .......10-6
10.4.4 Power-on Reset .......10-7
CHAPTER 11
SPECIAL OPERATING MODES
11.1 GENERAL 11-1
11.2 POWER CONTROL REGISTER . 11-1
11.2.1 Serial I/O Control Bits 11-1
11.2.2 Power Off Flag .11-1
11.3 IDLE MODE..... 11-4
11.3.1 Entering Idle Mode ...11-4
11.3.2 Exiting Idle Mode .....11-5
11.4 POWERDOWN MODE. 11-5
11.4.1 Entering Powerdown Mode 11-6
11.4.2 Exiting Powerdown Mode ..11-6
11.5 ON-CIRCUIT EMULATION (ONCE) MODE ..... 11-7
11.5.1 Entering ONCE Mode 11-7
11.5.2 Exiting ONCE Mode .11-7
CHAPTER 12
EXTERNAL MEMORY INTERFACE
12.1 EXTERNAL MEMORY INTERFACE SIGNALS 12-1
12.2 CONFIGURING THE EXTERNAL MEMORY INTERFACE..... 12-2
12.2.1 Page Mode and Nonpage Mode (PAGE Bit) .12-3
12.2.2 RD#, PSEN#, and the Number of External Address Pins (Bits RD1:0) .....12-3
12.2.2.1 Sixteen External Address Bits and a Single Read Signal
(RD1 = 1, RD0 = 0) ..12-4
12.2.2.2 Seventeen External Address Bits and a Single Read Signal
(RD1 = 0, RD0 = 1) ..12-4
12.2.2.3 Sixteen External Address Bits and Two Read Signals
(RD1 = 1, RD0 = 1) ..12-5
12.2.3 Wait States (WSA, WSB, XALE) .....12-6
12.2.4 Mapping On-chip Code Memory to Data Memory (87C251SB/83C251SB) ...12-7
12.3 EXTERNAL BUS CYCLES..... 12-7
12.3.1 Inactive External Bus .12-7
12.3.2 Bus Cycle Definitions .12-8
12.3.3 Nonpage Mode Bus Cycles ....12-8
12.3.4 Page Mode Bus Cycles ....12-10
12.4 WAIT STATES.... 12-13
12.4.1 Extending PSEN#/RD#/WR# 12-13
12.4.2 Extending ALE .......12-14
12.5 PORT 0 AND PORT 2 STATUS  12-15
12.5.1 Port 0 and Port 2 Pin Status in Nonpage Mode ...12-15
12.5.2 Port 0 and Port 2 Pin Status in Page Mode .12-16
12.6 EXTERNAL MEMORY DESIGN EXAMPLES. 12-16
12.6.1 Nonpage Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .12-16
12.6.1.1 An Application Requiring Fast Access to the Stack .12-16
12.6.1.2 An Application Requiring Fast Access to Data 12-17
12.6.2 Nonpage Mode, 128 Kbytes External RAM .12-19
12.6.3 Page Mode, 128 Kbytes External Flash .....12-21
12.6.4 Page Mode, 64 Kbytes External EPROM, 64 Kbytes External RAM .......12-21
12.6.5 Page Mode, 64 Kbytes External Flash, 32 Kbytes External RAM ....12-22
12.7 EXTERNAL BUS AC TIMING SPECIFICATIONS.... 12-24
12.7.1 Explanation of AC Symbols ..12-28
12.7.2 AC Timing Definitions ......12-28
CHAPTER 13
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
13.1 GENERAL 13-1
13.2 PROGRAMMING AND VERIFYING MODES... 13-2
13.3 GENERAL SETUP 13-3
13.4 OTPROM PROGRAMMING ALGORITHM....... 13-4
13.5 VERIFY ALGORITHM... 13-5
13.6 PROGRAMMABLE FUNCTIONS 13-5
13.6.1 On-chip Code Memory .......13-5
13.6.2 Configuration Bytes ..13-6
13.6.3 Lock Bit System .......13-9
13.6.4 Encryption Array ....13-10
13.6.5 Signature Bytes ......13-10
13.7 VERIFYING THE 83C251SB (ROM) . 13-10
13.8 VERIFYING THE 80C251SB (ROMLESS)..... 13-11
APPENDIX A
INSTRUCTION SET REFERENCE
A.1 NOTATION FOR INSTRUCTION OPERANDS. A-2
A.2 OPCODE MAP AND SUPPORTING TABLES .. A-4
A.3 INSTRUCTION SET SUMMARY A-11
A.3.1 Execution Times for Instructions that Access the Port SFRs ...... A-11
A.3.2 Instruction Summaries ..... A-14
A.4 INSTRUCTION DESCRIPTIONS ....... A-26
FIGURES
Figure Page
2-1 Functional Block Diagram of the 8XC251SB.....2-2
2-2 The CPU.2-5
2-3 8XC251SB Timing.2-6
3-1 Address Spaces for MCS® 251 Microcontrollers.3-1
3-2 Address Spaces for the MCS® 51 Architecture.3-3
3-3 Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture.3-4
3-4 8XC251SB Memory Space .....3-7
3-5 The Register File ...3-9
3-6 Dedicated Registers in the Register File and their Corresponding SFRs......3-11
4-1 Binary Mode Opcode Map.......4-3
4-2 Source Mode Opcode Map .....4-3
4-3 Program Status Word Register...4-19
4-4 Program Status Word 1 Register4-20
5-1 Interrupt Control System .5-2
5-2 Interrupt Enable Register 5-6
5-3 Interrupt Priority High Register 5-8
5-4 Interrupt Priority Low Register.5-8
5-5 The Interrupt Process....5-9
5-6 Response Time Example #1 .5-11
5-7 Response Time Example #2 .5-12
6-1 Port 1 and Port 3 Structure......6-3
6-2 Port 0 Structure 6-3
6-3 Port 2 Structure 6-4
6-4 Internal Pullup Configurations .6-6
7-1 Basic Logic of the Timer/Counters .......7-2
7-2 Timer 0/1 in Mode 0 and Mode 1 .7-4
7-3 Timer 0/1 in Mode 2, Auto-Reload7-5
7-4 Timer 0 in Mode 3, Two 8-bit Timers....7-6
7-5 TMOD: Timer/Counter Mode Control Register ..7-7
7-6 TCON: Timer/Counter Control Register ....7-8
7-7 Timer 2: Capture Mode .7-11
7-8 Timer 2: Auto Reload Mode (DCEN = 0).7-12
7-9 Timer 2: Auto Reload Mode (DCEN = 1).7-13
7-10 Timer 2: Clock Out Mode.......7-15
7-11 T2MOD: Timer 2 Mode Control Register.7-16
7-12 T2CON: Timer 2 Control Register ......7-17
8-1 Programmable Counter Array..8-3
8-2 PCA 16-bit Capture Mode .......8-6
8-3 PCA Software Timer and High-speed Output Modes..8-8
8-4 PCA Watchdog Timer Mode..8-10
8-5 PCA 8-bit PWM Mode .8-11
8-6 PWM Variable Duty Cycle .....8-12
8-7 CMOD: PCA Timer/Counter Mode Register....8-13
8-8 CCON: PCA Timer/Counter Control Register..8-14
Figure Page
8-9 CCAPMx: PCA Compare/Capture Module Mode Registers...8-16
9-1 Serial Port Block Diagram .......9-2
9-2 Serial Port Special Function Register...9-3
9-3 Mode 0 Timing..9-5
9-4 Data Frame (Modes 1, 2, and 3) ..9-6
9-5 Timer 2 in Baud Rate Generator Mode ...9-13
10-1 Minimum Setup ...10-1
10-2 CHMOS On-chip Oscillator....10-3
10-3 External Clock Connection ....10-4
10-4 External Clock Drive Waveforms10-5
10-5 Reset Timing Sequence 10-8
11-1 Power Control (PCON) Register.11-2
11-2 Idle and Powerdown Clock Control ....11-3
12-1 Internal and External Memory Spaces for RD1 = 1, RD0 = 0.12-4
12-2 Internal and External Memory Spaces for RD1 = 0, RD0 = 1.12-5
12-3 Internal and External Memory Spaces for RD1 = 1, RD0 = 1.12-6
12-4 External Code Fetch or Data Read Bus Cycle (Nonpage Mode) .....12-9
12-5 External Write Bus Cycle (Nonpage Mode).....12-9
12-6 Bus Structure in Nonpage Mode and Page Mode...12-10
12-7 External Code Fetch Bus Cycle (Page Mode).12-11
12-8 External Data Read Bus Cycle (Page Mode) 12-12
12-9 External Write Bus Cycle (Page Mode) .12-12
12-10 External Code Fetch or Data Read Bus Cycle with One PSEN#/RD#
Wait State (Nonpage Mode) 12-13
12-11 External Write Bus Cycle with One WR# Wait State (Nonpage Mode) .......12-14
12-12 External Code Fetch or Data Read Bus Cycle with One ALE Wait State
(Nonpage Mode) .......12-14
12-13 80C251SB in Nonpage Mode with External EPROM and RAM.....12-17
12-14 The Memory Space for the Systems of Figure 12-13 and Figure 12-18 .....12-18
12-15 87C251SB/83C251SB in Nonpage Mode with 128 Kbytes of External RAM...12-19
12-16 The Memory Space for the System of Figure 12-1512-20
12-17 80C251SB in Page Mode with External Flash.12-21
12-18 80C251SB in Page Mode with External EPROM and RAM .12-22
12-19 80C251SB in Page Mode with External Flash and RAM......12-23
12-20 The Memory Space for the System of Figure 12-1912-24
12-21 External Bus Cycles for Data/Instruction Read and Data Write in
Nonpage Mode..12-25
12-22 External Bus Cycles for Data Read and Data Write in Page Mode12-26
12-23 External Bus Cycles for Instruction Read in Page Mode......12-27
13-1 Setup for Programming and Verifying 13-3
13-2 OTPROM Programming Waveforms..13-4
13-3 Configuration Byte 0....13-7
13-4 Configuration Byte 1....13-8
13-5 OTPROM Timing.......13-11
2-1 Summary of 8XC251SB Features 2-4
3-1 Address Mappings.3-4
3-2 Register Bank Selection 3-8
3-3 Dedicated Registers in the Register File and their Corresponding SFRs......3-12
3-4 8XC251SB SFR Map and Reset Values .3-13
3-5 Core SFRs......3-14
3-6 I/O Port SFRs .3-14
3-7 Serial I/O SFRs ...3-15
3-8 Timer/Counter and Watchdog Timer SFRs .....3-15
3-9 Programmable Counter Array (PCA) SFRs.....3-15
4-1 Examples of Opcodes in Binary and Source Modes ...4-2
4-2 Data Types .......4-4
4-3 Notation for Byte Registers, Word Registers, and Dword Registers ..4-5
4-4 Addressing Modes for Data Instructions in the MCS® 51 Architecture ...4-6
4-5 Addressing Modes for Data Instructions in the MCS® 251 Architecture .4-7
4-6 Bit-addressable Locations .....4-13
4-7 Addressing Two Sample Bits.4-13
4-8 Addressing Modes for Bit Instructions4-14
4-9 Addressing Modes for Control Instructions......4-15
4-10 Compare-conditional Jump Instructions ..4-16
4-11 The Effects of Instructions on the PSW and PSW1 Flags......4-18
5-1 Interrupt System Pin Signals ...5-1
5-2 Interrupt System Special Function Registers ....5-3
5-3 Interrupt Control Matrix..5-4
5-4 Level of Priority.5-7
5-5 Interrupt Priority Within Level ..5-7
5-6 Interrupt Latency Variables ...5-13
5-7 Actual vs. Predicted Latency Calculations.......5-13
6-1 Input/Output Port Pin Descriptions .......6-1
6-2 Instructions for External Data Moves....6-8
7-1 Timer/Counter and Watchdog Timer SFRs .......7-2
7-2 External Signals ....7-3
7-3 Timer 2 Modes of Operation..7-15
8-1 PCA Special Function Registers (SFRs) ...8-4
8-2 External Signals ....8-4
8-3 PCA Module Modes ....8-15
9-1 Serial Port Signals.9-1
9-2 Serial Port Special Function Registers.9-2
9-3 Summary of Baud Rates .......9-10
9-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 39-12
9-5 Selecting the Baud Rate Generator(s) ....9-13
9-6 Timer 2 Generated Baud Rates .9-14
11-1 Pin Conditions in Various Modes11-3
12-1 External Memory Interface Signals.....12-1
12-2 Configuration Bits RD1:0.......12-3
12-3 Wait State Selection ....12-6
12-4 Bus Cycle Definitions (No Wait States) ...12-8
12-5 Port 0 and Port 2 Pin Status In Normal Operating Mode......12-15
12-6 AC Timing Symbol Definitions..12-28
12-7 AC Timing Definitions for Specifications on the 8XC251SB.12-29
12-8 AC Timing Definitions for Specifications on the Memory System...12-30
13-1 Programming and Verifying Modes ....13-2
13-2 Configuration Byte Values for 80C251SB and 80C251SB-1613-9
13-3 Lock Bit Function.13-9
13-4 Contents of the Signature Bytes.......13-10
13-5 OTPROM Timing Definitions ....13-12
A-1 Notation for Register Operands... A-2
A-2 Notation for Direct Addresses. A-3
A-3 Notation for Immediate Addressing ..... A-3
A-4 Notation for Bit Addressing..... A-3
A-5 Notation for Destinations in Control Instructions  A-3
A-6 Instructions for MCS® 51 Microcontrollers ....... A-4
A-7 New Instructions for the MCS® 251 Architecture ....... A-5
A-8 Data Instructions .. A-6
A-9 High Nibble, Byte 0 of Data Instructions... A-6
A-10 Bit Instructions. A-7
A-11 Byte 1 (High Nibble) for Bit Instructions... A-7
A-12 PUSH/POP Instructions . A-8
A-13 Control Instructions ..... A-8
A-14 Displacement/Extended MOVs.... A-9
A-15 INC/DEC A-10
A-16 Encoding for INC/DEC . A-10
A-17 Shifts ... A-10
A-18 State Times to Access the Port SFRs .... A-12
A-19 Summary of Add and Subtract Instructions.... A-14
A-20 Summary of Compare Instructions.... A-15
A-21 Summary of Increment and Decrement Instructions  A-16
A-22 Summary of Multiply, Divide, and Decimal-adjust Instructions A-16
A-23 Summary of Logical Instructions ....... A-17
A-24 Summary of Move Instructions.. A-19
A-25 Summary of Exchange, Push, and Pop Instructions  A-22
A-26 Summary of Bit Instructions.. A-23
A-27 Summary of Control Instructions ....... A-24
A-28 Flag Symbols. A-26
B-1 Signals Arranged by Functional Categories ..... B-1
B-2 Description of Columns of Table B-3... B-2
B-3 Signal Descriptions....... B-2
C-1 8XC251SB Special Function Registers (SFRs)C-1