uPSD3200系列使用指南

UPSD HARDWARE DESCRIPTION . 8
Figure 1. uPSD32xx Functional Modules   . 8
Special Function Registers (SFR)   9
MCU Module Registers   . . . 9
PSD Module Registers   . . . 9
Figure 2. Memory Map and Address Space  . . . . 9
Table 1. SFR Memory Map  . . . 10
Table 2. PSD Module Register Address Offset  11
MCU MODULE. . . . 13
TIMERS/COUNTERS   . 14
Timer 0 and Timer 1  . . . . 14
Mode 0. . . 14
Figure 3. Timer/Counter Mode 0: 13-bit Counter  14
Mode 1. . . 14
Mode 2. . . 15
Figure 4. Timer/Counter Mode 2: 8-bit Auto-reload  . 15
Mode 3. . . 15
Figure 5. Timer/Counter Mode 3: Two 8-bit Counters. . 15
Timer 2 . . 16
16-bit Capture. . 16
Figure 6. Timer 2 in Capture Mode  16
16-bit Auto-reload   . 17
Figure 7. Timer 2 in Auto-Reload Mode   . 17
Baud Rate Generator   . . . 17
Special Function Registers for Use with the Timers. 18
Table 3. Control Register for Timer0 and Timer1 (TCON)  18
Table 4. Timer Mode Register for Timer0 and Timer1 (TMOD) . 18
Table 5. Control Register for Timer2 (T2CON)  18
INTERRUPT SYSTEM  . 19
Figure 8. Interrupt System  . . . . 19
Table 6. Special Function Registers for Use with the Interrupt System . 20
Interrupt Priority   . 20
Table 7. Priority Levels and Vector Addresses  20
Interrupt Enable Structure  . . . 21
Table 8. Description of the IE Bits   21
Table 9. Description of the IEA Bits   . . . . 21
PULSE WIDTH MODULATION (PWM)  22
Figure 9. Four-Channel, 8-bit PWM Block Diagram  . 22
How to Determine the Pulse-width-ratio of the PWM Output  23
How to Determine the Repetition Frequency of the PWM Output . 23
How to Determine the Polarity of the PWM Output. . 23
How to Determine the Input Clock Frequency to the 8-bit counter of PWM4  . . . 23
How to Determine the Period and Pulse Width of the PWM4 Output  23
Figure 10.PWM4 With Programmable Pulse Width and Frequency  . . 23
How to Determine the Polarity of the PWM4 Output. 23
Figure 11.Programmable PWM4 Channel Block Diagram   24
Table 10. Special Function Registers for Use with the PWM  . . . 25
SUPERVISORY FUNCTION (LVD AND WATCHDOG)  . 26
Figure 12.RESET Configuration  26
Watchdog Timer – SFR   . 26
Table 11. Description of the WDRST Bits   26
Table 12. Description of the WDKEY Bits   26
Figure 13.RESET Pulse Width  . 27
STANDARD SERIAL INTERFACE UART   . . 28
Table 13. Description of the SCON and SCON2 Bits  28
Four Operation Modes   . 29
Mode 0. . . 29
Figure 14.Serial Port Mode 0 Waveforms   29
Mode 1. . . 29
Figure 15.Serial Port Mode 1 Waveforms   29
Mode 2. . . 30
Figure 16.Serial Port Mode 2 Waveforms   30
Mode 3. . . 30
Figure 17.Serial Port Mode 3 Waveforms   30
UART Baud Rates   31
Using Timer 1 to Generate Baud Rates   . 31
Using Timer 2 to Generate Baud Rates   . 31
POWER-SAVING MODES   . . 32
Table 14. Changes of Activity on Entering a Power-Saving Mode  32
Idle Mode 32
Table 15. Power Control Register, PCON  32
Power-down Mode  33
I²C BUS INTERFACE   . 34
Figure 18.Block Diagram of the I2C Bus Serial I/O  . . 34
S1CON or S2CON,   35
Table 16. Serial Control Register (S1CON, S2CON)  35
Table 17. Description of the S1CON and S2CON Bits. . 35
S1STA or S2STA,   . 36
Table 18. Serial Status Register (S1STA, S2STA)  . . 36
Table 19. Description of the S1STA and S2STA Bits  36
S1DAT or S2DAT,   . 36
Table 20. Data Shift Register (S1DAT, S2DAT)  36
S1ADR or S2ADR,   36
Table 21. Address Register (S1ADR, S2ADR)  . 36
USB BUS. . . . 37
Summary of the USB Standard   . 37
Figure 19.USB Bus Topology  . . 37
Figure 20.USB Bulk Transaction – 1   . . . . 38
Table 22. USB Bulk Transaction  38
Figure 21.USB Bulk Transaction – 2   . . . . 38
Figure 22.USB Interrupt Transaction  . . . . 39
USB Low-speed Device  . 40
Figure 23.Device Termination – Full-speed . . . . 40
Figure 24.Device Termination – Low-speed  . . . 40
Figure 25.USB Input/Output Design inside the uPSD32xxA  . . . . 41
Figure 26.Typical USB Connection Circuit for 5V (uPSD32xx) Systems . 41
Special Control Registers . . . . 42
Table 23. USB SFR Memory Map   . 42
Table 24. USB Address Register (UADR: 0EEh)  43
Table 25. Description of the UADR Bits  . . 43
Table 26. USB Interrupt Enable Register (UIEN: 0E9h). 43
Table 27. Description of the UIEN Bits   . . 43
Table 28. USB Interrupt Status Register (UISTA: 0E8h). 44
Table 29. Description of the UISTA Bits   . 44
Table 30. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)  45
Table 31. Description of the UCON0 Bits   45
Table 32. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)   . 46
Table 33. Description of the UCON1 Bits   46
Table 34. USB Control Register (UCON2: 0ECh)  46
Table 35. Description of the UCON2 Bits   46
Table 36. USB Endpoint0 Status Register (USTA: 0EDh)  . 47
Table 37. Description of the USTA Bits   . . 47
Table 38. USB Endpoint0 Data Receive Register (UDR0: 0EFh)  47
Table 39. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)  47
Table 40. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)  47
Table 41. USB Prescaler Register (USCL: 0E1h)  47
DDC INTERFACE. . 48
Figure 27.DDC Interface Block Diagram   . 48
Table 42. DDCCON Register (DDCCON)   49
Table 43. Description of the DDCCON Register Bits . 49
Table 44. SWNEB Bit Function  . 50
Figure 28.Transmit Mode Waveform  . . . . 50
Figure 29.Read Mode Sequence 51
Figure 30.Transmission Protocol in the DDC1 Interface. 52
ON-CHIP OSCILLATOR CIRCUIT  . 53
Figure 31.Pierce Oscillator  . . . . 53
Figure 32.Driving μPSD Clock from an Oscillator or an External Source  53
ANALOG-TO-DIGITAL CONVERTOR (ADC)  . . . . 54
Figure 33.A/D Block Diagram  . . 54
ADC-Related Special Function Registers  . . . 55
Table 45. ADC Special Function Register, Memory Map55
Table 46. Description of the ACON Bits   . 55
ADC Interrupts. 55
I/O PORTS (MCU MODULE)  . 56
Table 47. I/O Port Functions  . . . 56
Table 48. P1SFS (91h)   . . 56
Table 49. P3SFS (93h)   . . 56
Table 50. P4SFS (94h)   . . 56
PSD MODULE.. . . . 57
MEMORY BLOCKS.58
Primary Flash Memory and Secondary Flash Memory   58
Ready/Busy (PC3)  . 58
Flash Memory Sector Protect  . . 58
Table 51. Flash Protection Register   . . . . 58
Table 52. Secondary Flash Protection Register  58
Table 53. Instructions   . . . 59
SRAM . . . 60
Memory Addressing   . . . 60
Priority . . . 60
Figure 34.Priority Level of Memory and I/O Components in the PSD Module   . 60
VM Register.. . . 60
Table 54. VM Register   . . . 60
Figure 35.Combined Space Mode  . 61
Flexibility . 61
Figure 36.Different Splits of Memory to Meet Application Demands  . . 61
Page Register. . 62
Figure 37.Page Register Increases the Effective Core Space  . . 62
PLD BLOCKS 63
Figure 38.PLD Diagram  . . 63
Table 55. DPLD and CPLD Inputs  . 64
Decode PLD (DPLD)   . . . 65
Figure 39.Decode PLD (DPLD)  . 65
Complex PLD (CPLD)   . . 66
Figure 40.Macrocell and I/O Port 66
Output Macrocells (OMC)  . . . . 67
Figure 41.CPLD Output Macrocell  . 67
Product Term Allocator  . 68
Input Macrocells (IMC)   . 68
Figure 42.Input Macrocell   68
I/O PORTS. . . 69
Figure 43.General I/O Port Architecture   . 69
Port Operating Modes   . . 70
Table 56. Port Operating Modes  70
Table 57. Port Operating Mode Settings   . 70
PLD I/O Mode. . 71
Address Out Mode  . 71
Peripheral I/O Mode   . . . . 71
Figure 44.Peripheral I/O Mode  . 71
Port Configuration Registers (PCR)   . . 72
Table 58. Port Configuration Registers (PCR) . . 72
Table 59. Port Pin Direction Control, Output Enable P.T. Defined  72
Table 60. Drive Register Pin Assignment   72
Port Data Registers   . . . . 73
Data In . . . 73
Data Out Register   . 73
Output Macrocells (OMC)   73
OMC Mask Register   . . . . 73
Input Macrocells (IMC)   . . 73
Enable Out.. . . . 73
Table 61. Port Data Registers  . . 73
Ports A and B.. 74
Figure 45.Port A and Port B Structure  . . . 74
Port C . . . 75
Figure 46.Port C Structure  75
Port D . . . 76
Figure 47.Port D Structure  76
POWER MANAGEMENT UNIT (PMU)   77
Stand-by Mode.77
Power-down Mode  77
Figure 48.APD Unit   77
Table 62. Power-down Mode’s Effect on Ports  . 78
Figure 49.Enable Power-down Flow Chart  . . . . 79
PSD Chip Select Input (CSI, PD2)   . . . . 79
Turbo Mode. . . 79
PMMR Registers   . 80
Table 63. Power Management Mode Register PMMR0. 80
Table 64. Power Management Mode Register PMMR2. 80
RESET TIMING. . . . 81
Figure 50.Reset (RESET) Timing   . 81
Table 65. Status During Power-on RESET, Warm RESET and Power-down Mode . . 81
IN SYSTEM PROGRAMMING (ISP)  82
Table 66. JTAG Enable Register  82
Table 67. Pin Descriptions for FlashLINK/RLINK Adapter Assembly  . 82
IN-APPLICATION PROGRAMMING (IAP)   . . 84
Figure 51.Before IAP  . . . . 84
Figure 52.During IAP  . . . . 84
Figure 53.After IAP   84
DEVELOPMENT TOOLS   . . . 85
Keil Software. . 85
Figure 54.Keil Software uVision2   . 85
NOHAU In-Circuit Emulator  . . 86
Figure 55.NOHAU In-Circuit Emulator  . . . 86
DK3200 Development Board from ST   . 87
Figure 56. 87
FlashLINK/RLINK JTAG ISP Cable  . . . . 88
Figure 57.Pinout for FlashLINK/RLINK Adapter and Target System . . 88
Figure 58.FlashLINK/RLINK Cable Assembly  . . 89
JTAG Gang Programmer  . . . . 89
Figure 59. 89
REVISION HISTORY  . . 89
Table 68. Document Revision History   . . . 89