ML671000用户手册

1 Preface .1
Chapter 1 Overview
1.1. Features 1-2
1.2. Block Diagram .......1-4
1.3. Pins.......1-5
1.3.1. Pin Descriptions1-6
1.3.2. Pin Structure ...1-11
1.3.3. Pin Treatment .1-12
Chapter 2 CPU
2.1. Overview...............2-2
2.2. CPU Operating States....2-2
2.3. Switching State.......2-2
2.4. Memory Formats ....2-2
2.5. Instruction Length ..2-3
2.6. Data Types .............2-3
2.7. Operating Modes....2-3
2.8. Registers................2-4
2.8.1. The ARM state register set 2-4
2.8.2. The Thumb state register set.2-6
2.8.3. The relationship between ARM and Thumb state registers 2-7
2.8.4. Accessing Hi registers in Thumb state.....2-7
2.9. The Program Status Registers .2-8
2.9.1. The condition code flags....2-8
2.9.2. The control bits.2-8
2.10. Exceptions...........2-10
2.10.1. Action on entering an exception ............2-10
2.10.2. Action on leaving an exception..............2-11
2.10.3. Exception entry/exit summary ...............2-11
2.10.4. FIQ2-12
2.10.5. IRQ................2-12
2.10.6. Software interrupt ..2-12
2.10.7. Undefined instruction ......2-12
2.10.8. Exception vectors ..2-13
2.10.9. Exception priorities2-13
2.11. Reset...2-14
Chapter 3 CPU Control Functions
3.1. Overview...............3-2
3.1.1. Pins .3-3
3.1.2. Control Registers .....3-3
3.2. Detailed Control Register Descriptions.........3-4
3.2.1. Standby Control Register (SBYCON).....3-4
3.2.2. Clock Control Register (CKCON)...........3-5
3.2.3. Clock Supply Wait Control Register (CKWTCON)...........3-6
3.2.4. Reset Status Register (RSTST)................3-7
3.3. System Resets.........3-8
3.3.1. Resetting with External Input .3-8
3.3.2. Resetting with Watchdog Timer Overflow........3-8
3.4. System Clock (SYSCLK)........3-9
Contents-2
3.5. Standby Modes.....3-10
3.5.1. HALT Mode ...3-10
3.5.2. STOP Mode....3-11
3.6. Clock Supply Delay.....3-12
Chapter 4 Interrupt Controller
4.1. Overview.4-2
4.1.1. Block Diagram .....4-3
4.1.2. Pins.....4-4
4.1.3. Control Registers..4-4
4.2. Interrupt Sources .......4-5
4.2.1. External FIQ Interrupt Requests.4-5
4.2.2. External Interrupt Requests...4-5
4.2.3. Internal Interrupt Requests ....4-5
4.2.4. Interrupt Sources, Interrupt Numbers, and Control Registers 4-6
4.3. Detailed Control Register Descriptions............4-8
4.3.1. Interrupt Number Register (INR) ................4-8
4.3.2. Current Interrupt Level Register (CILR).....4-8
4.3.3. Interrupt Request Level Register (IRLR) ....4-9
4.3.4. External FIQ Control Register (EFIQCON)4-9
4.3.5. External Interrupt Control Register (EIRCON)...4-10
4.3.6. Interrupt Request Registers (IRR0 and IRR1).....4-10
4.3.7. Interrupt Level Control Registers (ILCONn, n=0 to 5)........4-11
4.4. Interrupt Processing.4-12
4.4.1. External FIQ Interrupts .......4-12
4.4.1.1. Interrupt Sequence ........4-12
4.4.2. External and Internal Interrupts4-13
4.4.2.1. Interrupt Priority Levels4-13
4.4.2.2. Interrupt Sequence ........4-14
4.4.2.3. Interrupt Level Control Example ........4-15
4.5. Sampling Timing for External Interrupt Requests....4-17
4.6. Interrupt Latency .....4-19
4.7. Notes on Processing Interrupts.4-20
Chapter 5 I/O Ports
5.1. Overview...............5-2
5.1.1. Control Registers .....5-4
5.2. Detailed Control Register Descriptions.........5-5
5.2.1. Port Output Registers (POn, n=0 to 3).....5-5
5.2.2. Port Input Registers (PIn, n=0 to 3).........5-6
5.2.3. Port Mode Registers (PMn, n=0 to 3)......5-7
5.2.4. Port Function Selection Registers (PFSn, n=0 to 3) ...........5-8
Chapter 6 Time Base Generator
6.1. Overview...............6-2
6.1.1. Block Diagram..6-2
6.1.2. Control Registers .....6-3
6.2. Detailed Control Register Descriptions.........6-4
6.2.1. Watchdog Timer Control Register (WDTCON)6-4
6.2.2. Time Base Control Register (TBGCON).6-5
6.3. Time Base Generator Operation.6-6
6.3.1. Time Base Counter (TBC).6-6
6.3.2. Watchdog Timer (WDT) ...6-7
6.3.3. Watchdog Timer Overflow Interval (tWDT).....6-8
6.3.4. Watchdog Timer Operation ..6-9
6.3.5. Interval Timer Operation .6-11
Chapter 7 Timers
7.1. Overview...............7-2
7.1.1. Block Diagram..7-2
7.1.2. Pins .7-4
7.1.3. Control Registers .....7-5
7.2. Detailed Control Register Descriptions.........7-6
7.2.1. Flexible Timer Control Registers (TMnCON, n=0 to 1) ....7-6
7.2.2. General-Purpose Timer Control Registers (TMnCON, n=2 to 3)..7-7
7.2.3. Flexible Timer Status Registers (TMnST, n=0 to 1) ..........7-8
7.2.4. General-Purpose Timer Status Registers (TMnST, n=2 to 3)........7-8
7.2.5. Timer Counters (TMnC, n=0 to 3) ..........7-9
7.2.6. Timer Registers (TMnC, n=0 to 3) ..........7-9
7.2.7. Flexible Timer General-Purpose Registers (TMnGR, n=0 to 1)..7-10
7.2.8. Flexible Timer I/O Level Registers (TMnIOV, n=0 to 1) 7-11
7.2.9. Flexible Timer Output Registers (TMnOUT, n=0 to 1)....7-12
7.2.10. Timer Enable Register (TMEN) ............7-13
7.2.11. Timer Disable Register (TMDIS)..........7-14
7.3. Timer Operation ...7-15
7.3.1. Flexible Timer Operation 7-15
7.3.1.1. Auto Reload Timer Mode ................7-15
7.3.1.2. Compare Out Mode....7-16
7.3.1.3. Pulse Width Modulation (PWM) Mode.....7-17
7.3.1.4. Capture Mode ..7-18
7.3.2. General-Purpose Timer Operation.........7-18
7.3.3. Selecting Clock......7-19
7.3.4. Starting/Stopping Timer ..7-19
7.4. Timer I/O Timing.7-20
7.4.1. Sampling External Clock Signal ............7-20
7.4.2. Sampling Capture Trigger Input ............7-21
7.4.3. Timer Output Timing.......7-22
Chapter 8 Universal Asynchronous Receiver/Transmitter (UART)
8.1. Overview.8-2
8.1.1. Block Diagram .....8-3
8.1.2. Pins.....8-4
8.1.3. Control Registers..8-5
8.2. Detailed Control Register Descriptions............8-6
8.2.1. UART Buffer Register (RBR/THR)............8-6
8.2.2. UART Shift Registers (TSR and RSR) .......8-6
8.2.3. FIFO Control Register (FCR) ..8-7
8.2.4. Line Control Register (LCR).8-8
8.2.5. Line Status Register (LSR)..8-10
8.2.6. Modem Control Register (MCR) ..............8-13
8.2.7. Modem Status Register (MSR) 8-14
8.2.8. Scratch Pad Register (SCR) 8-15
8.2.9. Interrupt Identification Register (IIR) .......8-16
8.2.10. Interrupt Enable Register (IER) ..............8-18
8.2.11. Divisor Latch (DLL and DLM)...............8-19
Contents-4
8.2.12. Clock Select Register (CSR) 8-20
8.3. Interrupts during Buffered Operation .............8-21
8.3.1. Receive Interrupts .....8-21
8.3.2. Transmit Interrupts....8-23
8.4. Polled Operation......8-24
8.5. DMA Transfer Requests.8-24
8.5.1. TXRDY.............8-24
8.5.2. RXRDY.............8-25
Chapter 9 Serial Communications Interface (SCI)
9.1. Overview.9-2
9.1.1. Block Diagram .....9-3
9.1.2. Pins.....9-4
9.1.3. Control Registers..9-4
9.2. Detailed Control Register Descriptions............9-5
9.2.1. SCI Transmit Control Register (STCON) ...9-5
9.2.2. SCI Receive Control Register (SRCON) ....9-6
9.2.3. SCI Status Register (SCIST) .9-7
9.2.4. SCI Buffer Register (SBUF) .9-8
9.2.5. SCI Shift Registers......9-8
9.2.6. SCI Timer Counter (STMC) .9-8
9.2.7. SCI Timer Register (STMR) .9-9
9.2.8. SCI Timer Control Register (STMCON) ....9-9
9.3. Asynchronous (ASI) Operation 9-10
9.3.1. Calculating Baud Rate.........9-10
9.3.2. Frame Formats ...9-11
9.3.3. Transmitting Data......9-12
9.3.4. Receiving Data ...9-13
9.4. Clock Synchronous (CSI) Operation ..............9-14
9.4.1. Frame Formats ...9-14
9.4.2. Transmitting Data......9-14
9.4.2.1. Transmitting as Master .9-15
9.4.2.2. Transmitting as Slave....9-16
9.4.3. Receiving Data ...9-17
9.4.3.1. Receiving as Master......9-17
9.4.3.2. Receiving as Slave ........9-18
Chapter 10 Direct Memory Access Controller (DMAC)
10.1. Overview..............10-2
10.1.1. Block Diagram .10-2
10.1.2. Pins.10-4
10.1.3. Control Registers.....10-5
10.2. Detailed Control Register Descriptions........10-6
10.2.1. DMA Source Address Register 0 (DSAL0 and DSAH0)...10-6
10.2.2. DMA Destination Address Register 0 (DDAL0 and DDAH0) .....10-6
10.2.3. DMA Transfer Count Register 0 (DTC0) .........10-6
10.2.4. DMA Transfer Request Select Register 0 (DTRS0) ..........10-7
10.2.5. DMA Channel Mode Register 0 (DCM0) .........10-8
10.2.6. DMA Source Address Register 1 (DSAL1 and DSAH1).10-10
10.2.7. DMA Destination Address Register 1 (DDAL1 and DDAH1) ...10-10
10.2.8. DMA Transfer Count Register 1 (DTC1) .......10-10
10.2.9. DMA Transfer Request Select Register 1 (DTRS1) ........10-11
10.2.10. DMA Channel Mode Register 1 (DCM1) .....10-12
10.2.11. DMA Command Register (DCMD) ....10-14
10.2.12. DMA End Status Register (DMAEST) .........10-15
10.2.13. DMA Status Register (DMAST).........10-16
10.2.14. DMA Request Status Register (DREQST)....10-17
10.3. Operational Description .......10-18
10.3.1. Transfer Requests..10-18
10.3.2. Addressing Mode ..10-21
10.3.3. Transfer Modes .....10-23
10.3.4. Access Data Sizes .10-25
10.3.5. Channel Priority Order....10-25
10.3.6. DMA Transfer End Conditions .............10-25
10.4. DMA Transfer Timing .........10-27
10.4.1. DMA Transfer Start Timing.10-27
10.4.2. Examples of DMA transfer timing ........10-28
10.5. Usage Notes.........10-32
Chapter 11 Universal Serial Bus Device Controller (USBC)
11.1. Overview.............11-2
11.1.1. Block Diagram11-3
11.1.2. Pins ................11-4
11.1.3. Control Registers ...11-4
11.2. Detailed Control Register Descriptions.......11-6
11.2.1. Device Address Register (DVCADR) ...11-6
11.2.2. Device Status Register (DVCSTAT) .....11-6
11.2.3. Packet Error Register (PKTERR)..........11-7
11.2.4. FIFO Status Registers (FIFOSTATn, n=1 to 2)................11-8
11.2.5. Frame Number Register Pair (FRAMEMSB and FRAMELSB) .11-9
11.2.6. Endpoint Packet Ready Register (PKTRDY)11-10
11.2.7. Endpoint 0 Receive Byte Count Register (EP0RXCNT)11-12
11.2.8. Endpoint 1 Receive Byte Count Register (EP1RXCNT)11-12
11.2.9. Endpoint 2 Receive Byte Count Register (EP2RXCNT)11-13
11.2.10.Endpoint 3 Receive Byte Count Register Pair
(EP3RXCNTMSB and EP3RXCNTLSB).....11-14
11.2.11.Transmit FIFO Buffer Clear Register (CLRFIFO) .........11-15
11.2.12. Software Reset Register (SOFTRST) ..11-15
11.2.13.Request Setup Registers.11-16
11.2.14. Interrupt Enable Registers (INTENBLn, n=1 to 2) ........11-18
11.2.15. Interrupt Status Registers (INTSTATn, n=1 to 2) ..........11-19
11.2.16.Endpoint 2 DMA Control Register (DMACON2)..........11-22
11.2.17.Endpoint 2 DMA Interval Register (DMAINTVL2) ......11-22
11.2.18.Endpoint 3 DMA Control Register (DMACON3)..........11-23
11.2.19.Endpoint 3 DMA Interval Register (DMAINTVL3) ......11-24
11.2.20.Endpoint 0 Receive Control Register (EP0RXCON) .....11-24
11.2.21.Endpoint 0 Receive Data Toggle Register (EP0RXTGL) .........11-25
11.2.22.Endpoint 0 Receive Payload Register (EP0RXPLD) .....11-25
11.2.23.Endpoint 1 Control Register (EP1CON) .......11-26
11.2.24.Endpoint 1 Data Toggle Register (EP1TGL) 11-27
11.2.25.Endpoint 1 Payload Register (EP1PLD)........11-27
11.2.26.Endpoint 0 Transmit Control Register (EP0TXCON)....11-28
11.2.27.Endpoint 0 Transmit Data Toggle Register (EP0TXTGL)........11-28
11.2.28.Endpoint 0 Transmit Payload Register (EP0TXPLD) ....11-29
11.2.29.Endpoint 0 Status Register (EP0STAT) ........11-29
11.2.30.Endpoint 2 Control Register (EP2CON) .......11-30
11.2.31.Endpoint 2 Data Toggle Register (EP2TGL) 11-31
Contents-6
11.2.32.Endpoint 2 Payload Register (EP2PLD)........11-31
11.2.33.EP3 Endpoint 3 Control Register (EP3CON)11-32
11.2.34.Endpoint 3 Data Toggle Register (EP3TGL) 11-33
11.2.35.Endpoint 3 Payload Register Pair (EP3PLDLSB and EP3PLDMSB)........11-33
11.2.36.Endpoint 0 FIFO Buffer Register (EP0RXFIFO/EP0TXFIFO) 11-34
11.2.37.Endpoint 1 FIFO Buffer Register (EP1RXFIFO/EP1TXFIFO) 11-34
11.2.38.Endpoint 2 FIFO Buffer Register (EP2RXFIFO/EP2TXFIFO) 11-34
11.2.39.Endpoint 3 FIFO Buffer Register (EP3RXFIFO/EP3TXFIFO) 11-35
11.2.40.Wake-up Control Register (AWKCON)........11-35
11.3. Paired FIFO buffers Operation.11-36
11.3.1. Bulk (Interrupt) Transfers.11-36
11.3.2. Isochronous Transfers....11-37
11.4. DMA Transfer Control........11-39
11.4.1. Transfer Request Conditions ...............11-39
11.4.2. Transfer Request Timing ..11-40
11.5. Power Conservation Function 11-41
11.6. Usage Notes .......11-42
Chapter 12 External Memory Controller (XMC)
12.1. Overview.............12-2
12.1.1. Block Diagram12-3
12.1.2. Pins ................12-5
12.1.3. Control Registers ...12-6
12.1.4. Address Space 12-7
12.2. Detailed Control Register Descriptions.......12-9
12.2.1. Bus Width Control Register (BWCON) 12-9
12.2.2. WAIT Input Control Register (WICON).......12-10
12.2.3. Off Time Control Register (OTCON)..12-11
12.2.4. Programmable Wait Control Register (PWCON)...........12-12
12.2.5. Bus Access Control Register (BACON)........12-13
12.2.6. DRAM Bank 2 Control Register (DR2CON)12-14
12.2.7. DRAM Bank 3 Control Register (DR3CON)12-15
12.2.8. DRAM Bank 2 Access Timing Control Register (AT2CON)....12-16
12.2.9. DRAM Bank 3 Access Timing Control Register (AT3CON)....12-16
12.2.10.DRAM Bank 2 Programmable Wait Control Register (DW2CON)...........12-17
12.2.11.DRAM Bank 3 Programmable Wait Control Register (DW3CON)...........12-17
12.2.12.Refresh Timer Counter (RFTCN)........12-18
12.2.13.Refresh Cycle Control Register (RCCON)....12-18
12.2.14.Refresh Timing Control Register (RTCON)..12-19
12.2.15.Refresh Control Register (RFCON).....12-20
12.3. Accessing Address Space....12-22
12.3.1. Data Bus Width ...12-22
12.3.2. Accessing Bank 0/1 External Memory Space12-23
12.3.2.1. Basic Access ..12-23
12.3.2.2. Wait Cycles....12-24
12.3.2.3. Half-Word Access....12-25
12.3.3. Accessing Bank 2/3 External Memory (DRAM) Space .12-26
12.3.3.1. Address Multiplexing..12-26
12.3.3.2. Basic Access ..12-27
12.3.3.3. Wait Cycles....12-28
12.3.3.4. Half-Word Access....12-32
12.3.3.5. Fast page (Burst) Access.............12-33
12.3.3.6. Refresh Access.........12-33
Contents-7
12.3.4. External Memory Space Access for All Banks...............12-37
12.3.4.1. Off Time Control .....12-37
12.3.4.2. Store Buffer....12-38
12.3.5. Accessing Bank 0 Internal Memory Space ....12-39
12.4. Bus Arbitration...12-40
12.4.1. Bus Access Priority........12-40
12.4.2. Requesting and obtaining Access to External Bus........ -12-40
12.4.3. Bus Lock Operation.......12-42
12.5. Standby Modes...12-43
12.5.1. Shifting to HALT Mode 12-43
12.5.2. Shifting to STOP Mode .12-43
12.6. Connecting External Memory 12-44
12.6.1. Connecting ROM.12-44
12.6.2. Connecting SRAM.........12-46
12.6.3. Connecting DRAM........12-48
Chapter 13 Electrical Characteristics
13.1. Absolute Maximum Ratings ...13-2
13.2. Recommended Operating Conditions...........13-2
13.3. DC Characteristics.13-3
13.4. AC Characteristics.13-4
13.4.1. Clock Timing ...13-4
13.4.2. Control Signal Timing.......13-4
13.4.3. External Bus Timing .........13-5
13.5. Timing Diagram ....13-6
13.5.1. Clock Timing ...13-6
13.5.2. Control Signal Timing.......13-7
13.5.3. DMA Timing....13-8
13.5.4. nXWAIT Signal Input Timing ................13-8
13.5.5. External Bus Release Timing.13-9
13.5.6. Bank 0, 1 Write Cycle.....13-10
13.5.7. Bank 0, 1 Read Cycle......13-11
13.5.8. Bank 2, 3 Write Cycle.....13-12
13.5.9. Bank 2, 3 Read Cycle......13-13
13.5.10. CAS Before RAS (CBR) Refresh........13-13
13.5.11. Self-Refresh..13-14
Appendix
A. List of Control Registers...A-2
B. Sample Circuits.........A-8
B.1. Crystal Oscillation circuit.......A-8
B.2. USB Interface Circuit...A-9
B.3. JTAG Interface Circuit.........A-10
C. Package DimensionsA-11