长线或不适当的示波器探头测试微控制器输出信号对系统带来的不良

Siemens’ C166-Family is manufactured in advanced CMOS technology to achieve high
performance at low power consumption. There are no open drain outputs at standard data
and address busses and control signals like RD# or WR#. Output drivers have been
designed for full TTL compatibility (output LOW voltage max. 0.4V @ 2.4mA / 1.6mA and
HIGH voltage min. 2.4V @ -2.4mA / -1.6mA; refer to User’s Manual for respective
specification).
Problems may occur if under test conditions long wires or not suitable scope probes are
connected to an output pin. These devices will bring several capacitances and
inductances into the system which results in static and/or dynamic overload and flatten
signal edges. Signals will appear delayed at their destination e.g. WR# pin of on-board
memory causing serious timing problems or system failures.