CC1050 Errata Notes

Switching between certain combinations of frequency words (FREQ) in CC1050
may cause the PLL never to be able to lock. This is most likely to occur in
frequency hopping systems. A software fix solves the problem.
Description and reason for the problem
When a new frequency is selected by updating the FREQ registers or changing the
MAIN.F_REG bit, a non-valid value can be latched due to internal clock skew. This
non-valid value may put the PLL in a deadlock situation and prevent the PLL from
locking.
The deadlock situation can happen if the 3 most significant bits of the FREQ words
are different for the two frequencies. If the 3 most significant bits are equal, the
deadlock will not occur. To ensure that the most significant bits are equal, use the
same reference frequency divider value (REFDIV) for all channels.