TFP501 Data Sheet Errata

I2C drive strength.
ISSUE
The DC digital I/O specification values for the I
2
C lines on the TFP501 to support the EEPROM and
Data Display Channel (DDC) are not specified in the datasheet.  Also, the I2C requirement of VOL
0.4V max with 3mA sink on these lines is marginal.  The I2C related signals are not 5V tolerant, which
is specified in the datasheet.  The pin definition table has a statement about 10K pullup tolerance which
is not clear.  
 
BACKGROUND & RECOMMENDATIONS
The HDCP specification 1.0 requires an HDCP port (section 2.6, page 20) to exchange values “over
the I
2
C serial interface of the DVI interface”.  This specification references version 2.0 of the Philips
Semiconductor I
2
C bus specification.
 
The DVI specification version 1.0 specifies that the interface will contain a DDC lines.  Section 1.3.1
on page 8 requires DDC2B from DDC specification version 3.  
 
DDC version 3 defines DDC2B as I2C protocol.  Refer to sections 2.3.2, 2.4.2 and 3.1.2.1.   Section
6.1.6, electrical specifications indicate graphic controller (host) termination resistances of 1.5K ohms
minimum to 5V, or 3mA current source.  Additional 47K ohm pullup resistance is defined for the
clock line at the display end.  Since the protocols related to the HDCP port are I2C and since DDC2AB
is not required for DVI and HDCP, the TFP501 targets I
2
C specified levels.  Threshold voltages are not
found in the DDC specification.

E-DDC version 1 defines various DDC protocols referring to I
2
C.  Electrical definition remains the
same as DDC version 3 with pullup resistors of >1.5K and <2.2K ohm in the host except for 47K ohm
pullup resistance on the clock line in the display.
 
The I
2
C specification version 2.1 lists electrical specifications in table 4 on page 31 for standard and
fast mode devices.  For devices with Vdd > 2V, VOL1 is 0.4V max. with 3mA sink current.   Based on
characterization of limited samples of the TFP501, this specification is met under typical conditions.
 
In section 18, the I
2
C specification recognized the system need for level translation in bus systems. 
This section describes a level shifter using a MOSFET.  The use of “DDC” in the pin names on the
TFP501 is to indicate their function, not to specify they connect directly to the DDC lines of a system. 
While it was desired to have these pins 5V tolerant, this was not achieved in the TFP501.   Level
shifters as described in the I
2
C bus specification or other level translators will be needed for a system
implementation.  Level shifters of the type in the I2C specification are one shown in the latest
TFP403/501 reference design document.
 
I
2
C low level input voltages depend on the supply voltage level, 0.3Vdd or 1.5V max for a 5V system.  
The TFP501 will meet this level with good margin at the 3mA drive level.  Losses through the level
shifter, an additional level shifter at the transmitting system end, heavier loads and longer cables may
all reduce the margin in the system.
 
System designers should consider the external circuits needed to support compliance to the various
versions of DDC in their system design.