基于FPGA 的（3,6）LDPC 码并行译码器设计与实现

本文基于Altera的FPGA（StatixⅡ-EP2S30F484C3）架构，实现了码率为1/2，帧长为1008bits的规则（3,6）LDPC码译码器。所采用的最小-和算法相对于传统的和-积算法在不损失译码性能的前提下，降低了硬件实现的复杂度，设计的并行结构有效地解决了串行结构所带来译码延时过大的问题，最大译码速率可达到60Mbit/s。为LDPC码的实际应用奠定了良好的基础。
关键词：LDPC码；校验矩阵；最小和算法；FPGA

Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA ZHONG Yong-xin， DU Xing-min （The Engineering Institute,Air Force Engineering University,Xi’an 710038,China） Abstract：In this paper,a decoder for (3,6) regular LDPC codes with code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(StatixⅡ-EP2S30F484C3) of Altera. In compare with traditional sum-product algorithm,min-sum algorithm has close performance and reduces the complication of hardware.Parallel architectures solves the problem of long time delay in serial architectures effectively and can achieve a decoding rate of 50Mbps.It lays a good foundation for application of LDPC codes.
Key words：LDPC codes；Parity check matrix；Min-sum algorithm；FPGA