• ADAU1373

• EVAL-ADAU1373Z

static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
 
	[--snip--]
	{
		I2C_BOARD_INFO("adau1373", 0x1a),
	},
	[--snip--]
}

static int __init stamp_init(void)
{
	[--snip--]
	i2c_register_board_info(0, bfin_i2c_board_info,
				ARRAY_SIZE(bfin_i2c_board_info));
	[--snip--]
 
	return 0;
}
arch_initcall(board_init);

The ADAU1373 features two PLLs:

enum adau1373_pll {
    ADAU1373_PLL1 = 0,
    ADAU1373_PLL2 = 1,
};

Each PLLs input frequency can be selected from a variety of signals:

enum adau1373_pll_src {
    ADAU1373_PLL_SRC_MCLK1 = 0,
    ADAU1373_PLL_SRC_BCLK1 = 1,
    ADAU1373_PLL_SRC_BCLK2 = 2,
    ADAU1373_PLL_SRC_BCLK3 = 3,
    ADAU1373_PLL_SRC_LRCLK1 = 4,
    ADAU1373_PLL_SRC_LRCLK2 = 5,
    ADAU1373_PLL_SRC_LRCLK3 = 6,
    ADAU1373_PLL_SRC_GPIO1 = 7,
    ADAU1373_PLL_SRC_GPIO2 = 8,
    ADAU1373_PLL_SRC_GPIO3 = 9,
    ADAU1373_PLL_SRC_GPIO4 = 10,
    ADAU1373_PLL_SRC_MCLK2 = 11,
};

The input frequency must configured to be between 7813 and 27000000 Hz. The output frequency must be configured to be between 45158000 and 49152000. Configuring the PLL with other input or output frequency will fail.

The PLL runs at 1024 times the base sample rate. So for a 48000 Hz based sample rate you'd normally choose 49152000 Hz for the PLL output frequncey and for a 44100 Hz based sample rate 45158400 Hz.

The codec driver registers three DAIs:

• “adau1373-aif1” (Digital Audio Interface A)
• “adau1373-aif2” (Digital Audio Interface B)
• “adau1373-aif3” (Digital Audio Interface C)

The DAIs can either use PLL1 or PLL2 as source. When configuring a DAI its rate should be set to the rate of the source PLL.

enum adau1373_clk_src {
    ADAU1373_CLK_SRC_PLL1 = 0,
    ADAU1373_CLK_SRC_PLL2 = 1,
};

static int bfin_eval_adau1373_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	int ret;
	int pll_rate;
 
	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;
 
	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;
 
	switch (params_rate(params)) {
	case 48000:
	case 8000:
	case 12000:
	case 16000:
	case 24000:
	case 32000:
		pll_rate = 48000 * 1024;
		break;
	case 44100:
	case 7350:
	case 11025:
	case 14700:
	case 22050:
	case 29400:
		pll_rate = 44100 * 1024;
		break;
	default:
		return -EINVAL;
	}
 
	ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
			ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
	if (ret)
		return ret;
 
	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
			SND_SOC_CLOCK_IN);
 
	return ret;
}
 
static int bfin_eval_adau1373_codec_init(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	unsigned int pll_rate = 48000 * 1024;
	int ret;
 
	ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
			ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
	if (ret)
		return ret;
 
	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
			SND_SOC_CLOCK_IN);
 
	return ret;
}
static struct snd_soc_ops bfin_eval_adau1373_ops = {
	.hw_params = bfin_eval_adau1373_hw_params,
};
 
static struct snd_soc_dai_link bfin_eval_adau1373_dai = {
	.name = "adau1373",
	.stream_name = "adau1373",
	.cpu_dai_name = "bfin-i2s.0",
	.codec_dai_name = "adau1373-aif1",
	.platform_name = "bfin-i2s-pcm-audio",
	.codec_name = "adau1373.0-001a",
	.ops = &bfin_eval_adau1373_ops,
	.init = bfin_eval_adau1373_codec_init,
};

There is no dedicated Blackfin STAMP evaluation board for the ADAU1373. During test and driver development we used the EVAL-ADAU1373 board.

It can be easily wired to the Blackfin STAMP SPORT header.

Device Drivers  --->
[*] I2C support  --->
[*]   I2C Hardware Bus support  --->
***     I2C system bus drivers (mostly embedded / system-on-chip) ***
<*>       Blackfin TWI I2C support
(100)     Blackfin TWI I2C clock (kHz)

Enable ALSA SoC evaluation board driver:

Device Drivers  --->
 Sound card support  --->
   Advanced Linux Sound Architecture  --->
     ALSA for SoC audio support  --->
       Support for the EVAL-ADAU1373 boards on Blackfin eval boards

Connect the STAMP SPORT 0 port (P6) to the EVAL-ADAU1373 J23 and J28 headers.

Note that the SPORT has separate signals for the capture and playback clocks, while the ADAU1373 uses the same clock signals for both, so the EVAL-ADU1373 clock signal pins need to be connected to two STAMP pins each.

Load the driver and make sure the sound card is properly instantiated.

root:/> modprobe snd-bf5xx-i2s
root:/> modprobe snd-soc-bf5xx-i2s
root:/> modprobe snd-soc-adau1373
root:/> modprobe snd-soc-bfin-eval-adau1373
dma rx:3 tx:4, err irq:45, regs:ffc00800
asoc: ADAU1373 <-> bf5xx-i2s mapping ok

root:/> modprobe snd-pcm-oss
root:/> tone
TONE: generating sine wave at 1000 Hz...

root:/> arecord -f cd | aplay
Recording WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Playing WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo