• ADF4106

• EVAL-ADF4106SD1Z

This lab presents the steps to setup an environment for using the EVAL-ADF4106SD1Z evaluation board together with the BeMicro SDK USB stick, the Nios II Embedded Development Suite (EDS) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-ADF4106SD1Z Evaluation Board with the BeMicro SDK Platform.

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:

• a controller board, like the EVAL-SDP-CS1Z (SDP-S)
• an compatible Analog Devices SDP product evaluation board
• corresponding PC software

The EVAL-SDP-CS1Z controller board is Serial Interfaces Only, low cost, reduced functionality controller board. It has a USB to Serial Engine at its core. It connects to the PC through a USB 2.0 high speed port. The SDP-S has a single 120 pin connector and exposes SPI, I2C and GPIO interfaces to connected SDP daughter boards.

The EVAL-ADF4106SD1Z is designed to allow the user to evaluate the performance of the ADF4106 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4106 synthesizer, an SMA connector for the reference input, power supplies, and an RF output. There is also a footprint for a loop filter and a VCO on board.

The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

• ADF4106 Product Info - pricing, samples, datasheet
• EVAL-ADF4106SD1Z evaluation board user guide
• BeMicro SDK
• Nios II Embedded Development Suite (EDS)
• Micrium uC-Probe

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Below is presented the list of required hardware items:

• Arrow Electronics BeMicro SDK FPGA-based MCU Evaluation Board
• BeMicro SDK/SDP Interposer adapter board
• EVAL-ADF4106SD1Z evaluation board
• Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

Below is presented the list of required software tools:

• Quartus II Web Edition design software v11.0
• Nios II EDS v11.0
• uC-Probe run-time monitoring tool, version 2.5

The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.

The Micrium uC/Probe Trial version 2.5 is available via download from the web at http://micrium.com/tools/ucprobe/trial/. After installation add to the “Path” system variable the entry “%QUARTUS_ROOTDIR%/bin/“ on the third position in the list.

• Lab Design Files

Create a folder called “ADIEvalBoardLab” on your PC and extract the ADF4106_EvalBoardLab.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoardLab folder: FPGA, Software, ucProbeInterface, NiosCpu.

A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with printf() in order to determine whether or not their systems are running as expected. Micrium provides a unique tool named µC-Probe to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system. This section presents the steps required to install the Micrium uC-Probe software tool and to run the demonstration project for the ADI evaluation board. A description of the uC-Probe demonstration interface is provided.

Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.

Select uC-Probe options.

• Click on the uC-Probe icon on the top left portion of the screen.
• Click on the Options button to open the dialog box.

Set target board communication protocol as JTAG UART

• Click on the Communication tab icon on the top left portion of the dialog box
• Select the JTAG UART option.

Setup JTAG UART communication settings

• Select the JTAG-UART option from the Communication tab.
• Press the Open File button to select the JTAG Debug Information file (.jdi)
• Navigate to the ADIEvalBoardLab/FPGA folder and select the BeMicroSDK.jdi file. Press Open.
• Type the value 1 in the the Device Id window.

• Select uCProbe_uart(0) from the Instance Id pulldown menu.

• Press Apply and OK to exit the options menu. The embedded target has two UARTs. uC-Probe will be communicating with the uCProbe_uart.

• Click the Open option from the uC-Probe menu and select the file ADIEvalBoardLab/ucProbeInterface/ADF4106_Interface.wsp.

• Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the Quick Evaluation section, select the file ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file, otherwise select the file ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf to be loaded as a symbol file.

• Run the demonstration project by pressing the Play button.

The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-ADF4106SD1Z evaluation board.

Section A allows for the communication with the board to be activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. Before pressing the ON/OFF switch, make sure you select the desired Device Initialization Procedure. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.

Sections B, C and D allow for configuration of each latch on the ADF4106.

Section B allows for the configuration of the Reference Counter Latch. The LDP switch allows setting the number of consecutive cycles of phase delay that must occur before Lock Detect is Set (0 = 3 Cycles, 1 = 5 Cycles). ABP2 and ABP1 allow setting the AntiBackLash Pulse Width. The Slider allows setting the R Divider. Pressing the Write R button programs the R Counter latch.

Section C allows for the configuration of the N Counter Latch. The CP Gain switch allows toggling between different settings for the charge pump. The B Slider allows setting the B Counter value, while the A Slider allows setting the value for the A Counter. The Write N button programs the N Counter Latch.

Sections D allows programming both the Initialization Latch and the Function Latch. The CE, PD2 and PD1 switches are user to select the Power Down Mode. Current Setting 2 and Current Setting 1 sliders are used to set the value of Icp (mA). Timer Control sets the timeout in PFD CYCLES. MUXOUT slider is used to select different functions for the MUXOUT pin. Fastlock can be enabled by toggling the Fastlock EN switch, while the Counter RST switch is used to reset the counters. Pressing the Write Func button will program the Function Latch. Pressing the Write INIT button will program the Initialization Latch.