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采用Nios驱动的AD7606的CED1Z FPGA方案

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资料介绍

This version (26 Jan 2021 10:56) was approved by Ioana Chelaru.The Previously approved version (11 Jan 2021 09:35) is available.

CED1Z FPGA Project for AD7606 with Nios driver

Supported Devices

Evaluation Boards

Overview

This document presents the steps to setup an environment for using the EVAL-AD7606EDZ / EVAL-AD7606-6EDZ / EVAL-AD7606-4EDZ evaluation board together with the EVAL-CED Converter Evaluation and Development (CED) Board and the Nios II Embedded Development Suite (EDS). Below is presented a picture of the EVAL-AD7606 Evaluation Board with the CED1 board.

The CED1Z board is intended for use in evaluation, demonstration and development of systems using Analog Devices precision converters. It provides the necessary communications between the converter and the PC, programming or controlling the device, transmitting or receiving data over a USB link.

The AD7606 / AD7606-6 / AD7606-4 are 16-bit, 8/6/4 channel, simultaneous sampling Analog-to-Digital Data Acquisition systems (DAS). The parts contain analog input clamp protection, 2nd order anti-alias filter, track and hold amplifier, 16-bit charge redistribution successive approximation ADC, flexible digital filter, 2.5V reference and reference buffer and high speed serial and parallel interfaces. The AD7606, AD7606-6, AD7606-4 operate from a single 5V supply and can accommodate ± 10V and ±5V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5V. The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on chip filtering and high input impedance eliminates the need for driver op-amps and external bipolar supplies. The AD7606 anti-alias filter has a 3 dB cut off frequency of 22 kHz and provides 40 dB anti-alias rejection when sampling at 200ksps. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth.

More information

AD7605 Product Info - pricing, samples, datasheet
AD7606-6 Product Info - pricing, samples, datasheet
AD7605-4 Product Info - pricing, samples, datasheet
EVAL-AD7605EDZ / AD7605-6EDZ / AD7605-4EDZ evaluation board user guide, available when installing the reference software from the CD
AD7606 Product Info - pricing, samples, datasheet
AD7606-6 Product Info - pricing, samples, datasheet
AD7606-4 Product Info - pricing, samples, datasheet
EVAL-AD7606EDZ / AD7606-6EDZ / AD7606-4EDZ evaluation board user guide, available when installing the reference software from the CD
Nios II Embedded Development Suite (EDS)

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Hardware Items

Below is presented the list of required hardware items:

Analog Devices EVAL-CED Converter Evaluation and Development (CED) Board
Terasic USB Blaster
EVAL-AD7605EDZ evaluation board or
EVAL-AD7606-6EDZ evaluation board or
EVAL-AD7605-4EDZ evaluation board or
EVAL-AD7606EDZ evaluation board or
EVAL-AD7606-6EDZ evaluation board or
EVAL-AD7606-4EDZ evaluation board
Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

Software Tools

Below is presented the list of required software tools:

Quartus II Web Edition design software v11.0
Nios II EDS v11.0

The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.

Downloads

Evaluation Project Files

Extract the Lab Files

EVAL-AD7606EDZ Create a folder called “ADIEvalBoard” on your PC and extract the ad7606_evalboard.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoard folder: FPGA, Hdl, NiosCpu, Software and DataCapture .

Folder	Description
FPGA	Contains all the files necessary to program the CED1Z board in order to evaluate the ADC. By executing the script program_fpga.bat the FPGA will be programmed with the evaluation project. New Nios2 applications can be created using the files from this folder. The ip subfolder contains the HDL core for connecting the evaluation board to the CED1Z board , the software drivers for HAL in /hdl/src/HAL and the AD7606 registers in /hdl/src/inc
Hdl	Contains the source files for the AD7606 HDL driver: - The doc subfolder contains a brief documentation for the core. - The src subfolder contains the HDL source files. - The tb folder contains the sources of the core's testbench
NiosCpu	Contains the CED1Z Quartus evaluation project source files . The ip subfolder contains the AD7606 QSYS component
Software	Contains the source files of the Nios2 SBT evaluation project
DataCapture	Contains the script files used for data acquisition

Install the USB-Blaster Device Driver

The USB Blaster is used to program the FPGA on the CED1Z board and also for data exchange between the system and a PC. To install the driver plug the Terasic USB Blaster into one of the PCs USB ports. Your Windows PC will find the new hardware and try to install the driver.

Since Windows cannot locate the driver for the device the automatic installation will fail and the driver has to be installed manually. In the Device Manager right click on the USB-Blaster device and select Update Driver Software.

In the next dialog box select the option Browse my computer for driver software. A new dialog will open where it is possible to point to the driver’s location. Set the location to altera/11.0/quartus/drivers/usb-blaster and press Next.

If Windows presents you with a message that the drivers have not passed Windows Logo testing, please click “Install this driver software anyway”. Upon installation completion a message will be displayed to inform that the installation is finished.

30 Nov 2011 11:18 · Adrian Costina

AD7606 Evaluation Project Overview

The evaluation project contains all the source files needed to build a system that can be used to configure the AD7606 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcore controls the communication with the Device Under Test (DUT) and the data capture process. The captured data is saved into the SRAM of the CED1Z board and aftwerwards it is read by the PC application and saved into a comma separated values (.csv) file that can be used for further data analysis.

CED1Z FPGA Design

The following components are implemented in the FPGA design:

Name	Address	IRQ
CPU	0x00000800	-
PLL	0x00000000	-
ONCHIP_MEM	0x00002000	-
LEDS	0x00000010	-
SYSID	0x00000020	-
SRAM	0x00200000	-
TRISTATE_BRIDGE_0	-	-
JTAG_UART_0	0x00000030	1
SYS_TIMER	0x00000040	2
MM_CONSOLE_MASTER	-	-
PWR_DATA	0x00000060	-
I2C_INT	0x00000080	-
PWR_EN_CLK	0x000000a0	-
AD7606_0	0x000000c0	-
Table 1 System components

The Nios II processor contains a peripheral that implements the communication protocol with the DUT. The peripheral is divided into three logical modules: a module which implements the interface with the Avalon bus and the communication with the SRAM, a module which implements an Avalon master interface which is used to write data directly in the SRAM and a module which communicates with the AD7606.

Table 2 describes the port definitions of the Avalon peripheral:

Port	Direction	Width	Description
Generic pins
CLK_I	IN	1	System clock. Designed with a 98MHz clock
RESET_I	IN	1	System reset
Avalon Slave Interface
AVALON_WRITEDATA_I	IN	32	Slave write data bus
AVALON_WRITE_I	IN	1	Slave write data request
AVALON_READ_I	IN	1	Slave read data request
AVALON_ADDRESS_I	IN	3	Slave address bus
AVALON_READDATA_O	OUT	32	Slave read data bus
Avalon Master Interface
AVALON_MASTER_WAITREQUEST	IN	1	Master wait request signal
AVALON_MASTER_ADDRESS_O	OUT	32	Master address bus
AVALON_MASTER_WRITE_O	OUT	1	Master write signal
AVALON_MASTER_BYTEENABLE_O	OUT	2	Master byte enable signals
AVALON_MASTER_WRITEDATA_O	OUT	16	Master write data bus
External connectors
ADC_DB_I	IN	16	ADC data bus used to read data from the AD7606
ADC_BUSY_I	IN	1	ADC Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13th rising edge of CLKIN
ADC_OS_O	OUT	3	Oversampling Mode Pins. These inputs are used to select the oversampling ratio
ADC_RANGE_O	OUT	1	Analog Input Range Selection. The polarity of this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is +-10V for all channels. If this pin is tied to a logic low, the analog input range is +-5V. A logic change has immediate effect.
ADC_CS_N_O	OUT	1	ADC Chip Select. Active low logic input used in conjunction with RD to read conversion data.
ADC_RD_N_O	OUT	1	ADC Read pin. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low.
ADC_RESET_O	OUT	1	Reset pin. When set to logic high, the rising edge of RESET resets the AD7606.
ADC_STDBY_O	OUT	1	Standby Mode pin. This pin is used to place the AD7606 into one of the two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin.
ADC_CONVST_N_O	OUT	1	ADC conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in auto-shutdown or auto-standby modes, a rising edge on CONVST is used to power up the device.
Table 2 Port description

Table 3 describes the registers of the Avalon peripheral:

Name	Offset	Width	Access	Description
CONTROL_REGISTER	0	32	RW	Bit 0 is used to start data acquisition Bit 1 is used to initiate software reset of the core Bit 2 is used to configure the Avalon write master core to write data to the same location Bit 3 is used to write data to the AD7606 evaluation board
ACQ_COUNT_REGISTER	1	32	RW	Register used to configure the number of samples to be acquired when acquisition is started
BASE_REGISTER	2	32	RW	Register used to configure the base address of the memory location where the acquired data is to be written
STATUS	3	32	R	Bit 0 is used to signal that the acquisition is complete Bit 1 is used to signal that the internal memory buffer has been overflown Bit 2 is used to signal that the user has performed a write of a read only register register
DUT_WRITE_REGISTER	4	32	W	Register used to configure the driver submodule
Table 3 Register description

The follwing figure presents the timing diagram for the read operations from the AD7606 driver.

AD7606 module

This module is the actual driver of the AD7606 data acquisition system.

Port	Direction	Width	Description
General Connectors
FPGA_CLK_I	IN	1	48 MHz clock
ADC_CLK_I	IN	1	20 MHz clock
RESET_I	IN	1	Module reset
CED1Z_interface connectors
WR_DATA_N_I	IN	1	Signal used to write data in the driver’s internal registers
DATA_I	IN	16	Data bus, used configure the driver
DATA_O	OUT	16	Parallel bus to transfer the data to the upper module
DATA_RD_READY_O	OUT	1	Signals that at port DATA_O there is new data available
DATA_WR_READY_O	OUT	1	Signals that the write from upper module has been performed
SYNC_O	OUT	1	Signals that the next data transfer will correspond to channel 1
AD7606 connectors
ADC_DB_I	IN	16	ADC data bus used to read data from the AD7606
ADC_BUSY_I	IN	1	ADC Busy Output. Logic output that indicates the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY on the 13th rising edge of CLKIN
ADC_OS_O	OUT	3	Oversampling Mode Pins. These inputs are used to select the oversampling ratio
ADC_RANGE_O	OUT	1	Analog Input Range Selection. The polarity of this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is +-10V for all channels. If this pin is tied to a logic low, the analog input range is +-5V. A logic change has immediate effect.
ADC_CS_N_O	OUT	1	ADC Chip Select. Active low logic input used in conjunction with RD to read conversion data.
ADC_RD_N_O	OUT	1	ADC Read pin. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low.
ADC_RESET_O	OUT	1	Reset pin. When set to logic high, the rising edge of RESET resets the AD7606.
ADC_STDBY_O	OUT	1	Standby Mode pin. This pin is used to place the AD7606 into one of the two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin.
ADC_CONVST_N_O	OUT	1	ADC conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-down, when operating in auto-shutdown or auto-standby modes, a rising edge on CONVST is used to power up the device.
Table 4 Port description for the AD7606 module

Quick Evaluation

The next sections of this document present all the steps needed to create a fully functional project that can be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load in the FPGA an image that contains a fully functional system that can be used for platform evalution. The first step of the quick evaluation process is to program the FPGA with the image provided in the lab files. Before the image can be loaded the Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To load the FPGA image you must first make sure that the USB cable is not connected to the CED1Z board. Connect the USB Blaster to the J6 connector of the CED1Z and power the board. Run the program_fpga.bat batch file located in the ADIEvalBoard/FPGA folder.

In order to acquire data, follow the instructions in the Evaluation Project Data Acquisition section.

NIOS II Software Design

This section presents the steps for developing a software application that will run on the CED1Z system and will be used for controlling and monitoring the operation of the ADI evaluation board.

Create a new project using the NIOS II Software Build Tools for Eclipse

Launch the Nios II SBT from the Start → All Programs → Altera → Nios II EDS 11.0 → Nios II 11.0 Software Build Tools for Eclipse (SBT).

NOTE: Windows 7 users will need to right-click and select Run as administrator. Another method is to right-click and select Properties and click on the Compatibility tab and select the Run This Program As An Administrator checkbox, which will make this a permanent change.

1. Initialize Eclipse workspace

When Eclipse first launches, a dialog box appears asking what directory it should use for its workspace. It is useful to have a separate Eclipse workspace associated with each hardware project that is created in SOPC Builder. Browse to the ADIEvalBoard directory and click Make New Folder to create a folder for the software project. Name the new folder “eclipse_workspace”. After selecting the workspace directory, click OK and Eclipse will launch and the workbench will appear in the Nios II perspective.

2. Create a new software project in the SBT

Select File → New → Nios II Application and BSP from Template.

Click the Browse button in the SOPC Information File Name dialog box.
Select the uC.sopcinfo file located in the ADIEvalBoard/FPGA directory.
Set the name of the Application project to “ADIEvalBoard”.
Select the Blank Project template under Project template.
Click the Finish button.

The tool will create two new software project directories. Each Nios II application has 2 project directories in the Eclipse workspace.

The application software project itself - this where the application lives.
The second is the Board Support Package (BSP) project associated with the main application software project. This project will build the system library drivers for the specific SOPC system. This project inherits the name from the main software project and appends “_bsp” to that.

Since you chose the blank project template, there are no source files in the application project directory at this time. The BSP contains a directory of software drivers as well as a system.h header file, system initialization source code and other software infrastructure.

Configure the Board Support Package

Configure the board support package to specify the properties of this software system by using the BSP Editor tool. These properties include what interface should be used for stdio and stderr messages, the memory in which stack and heap should be allocated and whether an operating system or network stack should be included with this BSP.
Right click on the ADIEvalBoard_bsp project and select Nios II → BSP Editor… from the right-click menu.

The software project provided in this lab does not make use of an operating system. All stdout, stdin and stderr messages will be directed to the jtag_uart.

Select the Common settings view. In the Common settings view, change the following settings:
- Select the jtag_uart_0 for stdin, stdout and stderr messages. Note that you have more than one choice.
- Select none for the sys_clk_timer and timestamp_timer.

The memory used by the design is should be changed from OnChip ram to SRAM for the .text region.

Select Linker Script tab.
Change .text region Linker Region Name from onchip_mem to sram.

Select File → Save to save the board support package configuration to the settings.bsp file.
Click the Generate button to update the BSP.
When the generate has completed, select File → Exit to close the BSP Editor.

Configure BSP Project Build Properties

In addition to the board support package settings configured using the BSP Editor, there are other compilation settings managed by the Eclipse environment such as compiler flags and optimization level.

Right click on the ADIEvalBoard_bsp software project and select Properties from the right-click menu.
On the left-hand menu, select Nios II BSP Properties.
During compilation, the code may have various levels of optimization which is a tradeoff between code size and performance. Change the Optimization level setting to Level 2
Since our software does not make use of C++, uncheck Support C++.
Check the Reduced device drivers option
Check the Small C library option
Press Apply and OK to regenerate the BSP and close the Properties window.

Add source code to the project

In Windows Explorer locate the project directory which contains a directory called Software. In Windows Explorer select all the files and directories from the Software folder and drag and drop them into the Eclipse software project ADIEvalBoard.

Select all the files and folders and drag them over the ADIEvalBoard project in the SBT window and drop the files onto the project folder.

A dialog box will appear to select the desired operation. Select the option Copy files and folders and press OK.

This should cause the source files to be physically copied into the file system location of the software project directory and register these source files within the Eclipse workspace so that they appear in the Project Explorer file listing.

Configure Application Project Build Properties

Just as you configured the optimization level for the BSP project, you should set the optimization level for the application software project ADIEvalBoard as well.

Right click on the ADIEvalBoard software project and select Properties from the right-click menu.
On the left-hand menu, select the Nios II Application Properties tab
Change the Optimization level setting to Level 2.
Press Apply and OK to save the changes.

Define Application Include Directories

Application code can be conveniently organized in a directory structure. This section shows how to define these paths in the makefile.

In the Eclipse environment double click on my_include_paths.in to open the file.
Click the Ctrl and A keys to select all the text. Click the Ctrl and C keys to copy all the text.

Double click on Makefile to open the file.
If you see the message shown here about resources being out of sync, right click on the Makefile and select Refresh.

Select the line APP_INCLUDE_DIRS :=

Click the Ctrl and V keys to replace the selected line with the include paths.

Click the Ctrl and S keys to save the Makefile.

Compile, Download and Run the Software Project

1. Build the Application and BSP Projects

Right click the ADIEvalBoard_bsp software project and choose Build Project to build the board support package.
When that build completes, right click the ADIEvalBoard application software project and choose Build Project to build the Nios II application.

These 2 steps will compile and build the associated board support package, then the actual application software project itself. The result of the compilation process will be an Executable and Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.

In case an error appears at compile time with a description like : section .rodata loaded at [00400164,00400477] overlaps section .text loaded at [00400164,004054d7] the enable_alt_load_copy_exceptions option must be unchecked from BSP Editor → Main → Settings → Advanced→ hal.linker

2. Verify the Board Connection

The CED1Z hardware is designed with a System ID peripheral. This peripheral is assigned a unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC Builder also places this information in the .sopcinfo hardware description file. The BSP is built based on the information in the .sopcinfo file.

Select the ADIEvalBoard application software project.
Select Run → Run Configurations…
Select the Nios II Hardware configuration type.
Press the New button to create a new configuration.
Change the configuration name to CED1Z and click Apply.
On the Target Connection tab, press the Refresh Connections button. You may need to expand the window or scroll to the right to see this button.
Select the jtag_uart_0 as the Byte Stream Device for stdio.
Check the Ignore mismatched system ID option.
Check the Ignore mismatched system timestamp option.

3. Run the Software Project on the Target

To run the software project on the Nios II processor:

Before running the the software project, the FPGA located on the CED1Z must be programmed with the Nios II system image. To program the FPGA run the ADIEvalBoard/FPGA/program_fpga.bat script.
Press the Run button in the Run Configurations window. This will re-build the software project to create an up–to-date executable and then download the code into memory on the CED1Z hardware. The debugger resets the Nios II processor, and it executes the downloaded code. Note that the code is verified in memory before it is executed

The code size and start address might be different than the ones displayed in the above screenshot.

20 Aug 2012 16:26 · Adrian Costina

Evaluation Project Data Acquisition

After the FPGA is correctly programmed the data acquisition process can start by executing the data_capture.bat script. The data_capture.tcl file can be modified to acquire a variable number of channels, to change the oversampling signals and the range signal. If the number of channels is larger than the number of channels available on the part, the additional channels will be taken from channel 1. (e.g for AD7606-4, channel 5 will have the same data as channel 1, channel 6 will have the same data as channel 2 etc).

The configuration from data_capture.tcl is performed the first time the script is executed. If changes are performed after that, the system must be reinitialized by reprogramming the FPGA.

If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a different number of columns, each column corresponding to a channel.