DS26303短程线路接口单元与IDT82V2048的比较

摘要：本文比较了DS26303和IDT82V2048的不同，特别说明了如何在已有的IDT82V2048应用中使用DS26303，详细阐述了它们的特性区别、寄存器和硬件设计时的考虑。

概述

本文比较了DS26303和IDT82V2048的不同，特别阐述了如何在已有的IDT82V2048应用中使用DS26303。DS26303是一个单3.3V供电的8通道E1/T1/J1短程线路接口单元(LIU)。不需要更改软件就可以支持IDT82V2048的功能，并提供附加的特性。不需要改变PCB，DS26303就可以用在现有的IDT82V2048应用中，仅仅需要根据应用改变外围元器件值。

特性的区别分为三个不同部分：表1为DS26303具备而IDT82V2048不具备的一些特性；表2为IDT82V2048具备而DS26303不具备的一些特性。表3为DS26303和IDT82V2048共有但是在两个器件上实现不同的特性。

表6到表10为DS26303和IDT82V2048寄存器之间的不同以及DS26303附加寄存器组提供的附加功能。图1和表11为在现有的IDT82V2048应用中使用DS26303时需要对器件值所做的细微改变。

表1. DS26303不同于IDT82V2048的特性

DS26303	IDT82V2048
Programmable option to clear interrupt status on write or read. Clear on read is default.	Not supported.
Individual channel control for jitter attenuator: Enable/disable FIFO depth FIFO limit trip	All channels have global control.
Internal software-selectable transmit and receive-side termination for 100Ω T1 twisted-pair, 110Ω J1 twisted-pair, 120Ω E1 twisted-pair, and 75Ω E1 coaxial applications.	Not supported.
In HPS mode, the transmitter output and the internal impedance of the receiver can be turned off with only the OE pin.	Requires that both receivers use the same front-end termination.
Built in BERT tester for diagnostics.	Not supported.
Individual channel control for: Short-circuit protection AIS enable on LOS RCLK inversion TCLK inversion	All channels have global control.
Individual channel-line violation detection.	Not supported.
Flexible MCLK See Table 4 for available input frequencies.	Not supported.
Programmable TECLK output pin (1.544MHz or 2.048MHz)	Not supported.
Programmable CLKA output pin See Table 5 for available output frequencies.	Not supported.
Flexible interrupt pin	Not supported.

表2. IDT82V2048不同于DS26303的特性

DS26303	IDT82V2048
Uses single optimal value.	Capability to select the jitter attenuator bandwidth.
Not provided.	Inband loopack (loopup and loopdown codes).
MLCK Pin Functionality The DS26303 and IDT82V2048 both require MCLK to for data with clock recovery as well as AIS detection. The MCLK pin of the IDT82V2048 provides additional functionality not present in the DS26303. IDT82V2048 MCLK held high. The IDT82V2048 slices the incoming bipolar line signal into RZ pulse (data-recovery mode). IDT82V2048 MCLK held low. All the receivers are powered down, and the output pins RCLKn, RDPn, and RDNn are switched to high impedance. Note that wait state generation through RDY/ACK is not available if MCLK is not provided.

表3. DS26303和IDT82V2048的特性区别

DS26303	IDT82V2048
3.3V LIU power only, 5V not provided.	5V LIU power.
Non-mux Intel® write address to WRB rising-edge setup time is 17ns.	Non-mux Intel write address to WRB rising-edge setup time is 6ns.
Expects non-mux Intel read address to be valid when RDB is active.	Non-mux Intel read address to RDB rising-edge setup time is 6ns. This might be an error in data sheet because data is out before this setup time.
Inactive RDY to tri-state delay time 12ns (max).	Inactive RDY to tri-state delay time 3ns (max).
Clears the interrupt pin when reading or writing the interrupt status.	Clear interrupt pin by reading the corresponding status register.
Jitter attenuator FIFO depths of 32 bits or 128 bits.	Jitter attenuator FIFO depths of 32 bits or 64 bits.
Individual channel control for jitter attenuator: Enable/disable FIFO depth FIFO limit trip	All channels have global control.

表4. DS26303 MCLK的选择范围

PLLE	MPS1, MPS0	MCLK MHz (±50ppm)	FREQS	T1 or E1 Mode
0	xx	1.544	x	T1
0	xx	2.048	x	E1
1	00	1.544	1	T1/J1 or E1
1	01	3.088	1	T1/J1 or E1
1	10	6.176	1	T1/J1 or E1
1	11	12.352	1	T1/J1 or E1
1	00	2.048	0	T1/J1 or E1
1	01	4.096	0	T1/J1 or E1
1	10	8.192	0	T1/J1 or E1
1	11	16.384	0	T1/J1 or E1

表5. DS26303时钟A的选择范围

CLKA3 to CLKA0	MCLK (Hz)
0000	2.048M
0001	4.096M
0010	8.192M
0011	16.384M
0100	1.544M
0101	3.088M
0110	6.176M
0111	12.352M
1000	1.536M
1001	3.072M
1010	6.144M
1011	12.288M
1100	32k
1101	64k
1110	128k
1111	256k

寄存器的考虑事项

DS26303包括四个主要的寄存器组。

• 主寄存器组(DS26303和IDT82V2048)
• 二级寄存器组(DS26303和IDT82V2048)
• 独立LIU寄存器组(DS26303独有)
• BERT寄存器组(DS26303独有)

为了利用DS26303的附加特性和灵活性，必须在IDT82V2048应用的源代码中添加程序。地址指针控制寄存器(ADDP)的地址为1Fh，它被用作指针来访问不同的寄存器组。表6给出了DS26303寄存器组列表和访问这些寄存器组时所需要的ADDP值。

表6. DS26303地址指针选择

ADDP7 to ADDP0 (Hex)	Bank Name	DS26303	IDT82V2048
00	Primary Bank	Yes	Yes
AA	Secondary Bank	Yes	Yes
01	Individual LIU Bank	Yes	No
02	BERT Bank	Yes	No

DS26303的主寄存器组和IDT82V2048是一样的。如果使用DS26303替换现有的IDT82V2048，并且仅用到主寄存器组，则不需要修改应用软件。表7给出了主寄存器组列表。

表7. DS26303和IDT82V2048的主寄存器组

Address (Hex)	DS26303 and IDT82V2048
00–15	Primary Registers
16–1E	Reserved
1F	ADDP

尽管DS26303与IDT82V2048都提供二级寄存器组，但并不是所有寄存器及其相应功能都是一样的。表8给出了二级寄存器组包含的寄存器列表，以及它们在DS26303和IDT82V2048中实现的功能。

DS26303包含另外两个寄存器组：独立LIU寄存器组和BERT寄存器组。表9为独立LIU寄存器组包含的寄存器列表，表10为BERT寄存器组包含的寄存器列表。为了利用DS26303的附加特性和灵活性，必须在IDT82V2048应用的源代码中添加程序。

表8. DS26303的二级寄存器组

Address (Hex)	Register Name	DS26303	IDT82V2048
00	Single-Rail Mode Select	Yes	Yes
01	Line-Code Selection	Yes	Yes
02	Clock-Recovery Enable	No	Yes
03	Receiver Power-Down Enable	Yes	Yes
04	Transmitter Power-Down Enable	Yes	Yes
05	Excessive Zero-Detect Enable	Yes	Yes
06	Code-Violation-Detect Enable Bar	Yes	Yes
07	Receive Equalizer Enable	No	Yes
08	Inband Loopback (LB) Configuration	No	Yes
09	Inband LB Activation Code	No	Yes
0A	Inband LB Deactivation Code	No	Yes
0B	Inband LB Receive Status	No	Yes
0C	Inband LB Interrupt Mask	No	Yes
0D	Inband LB Interrupt Status	No	Yes
0E	Inband LB Activation/Deactivation Code Generator	No	Yes
1F	Set to AAh for access to Secondary Register Bank	Yes	Yes

表9. DS26303的独立LIU寄存器组

Address (Hex)	Register Name
00	Individual JA Enable
01	Individual JA Position Select
02	Individual JA FIFO Depth Select
03	Individual JA FIFO Limit Trip
04	Individual Short-Circuit Protection Disable
05	Individual AIS Select
06	Master-Clock Select
07	Global-Management Register
08–0F	Reserved
10	Bit-Error-Rate Tester Control Register
12	Line-Violation Detect Status
13	Receive-Clock Invert
14	Transmit-Clock Invert
15	Clock-Control Register
16	RCLK Disable Upon LOS Register
1E	Global-Interrupt Status Control
1F	Set to 01h for access to Individual LIU Register Bank

表10. DS26303的BERT寄存器组

Address (Hex)	Register Name
00	BERT Control Register
01	Reserved
02	BERT Pattern Configuration 1
03	BERT Pattern Configuration 2
04	BERT Seed/Pattern 1
05	BERT Seed/Pattern 2
06	BERT Seed/Pattern 3
07	BERT Seed/Pattern 4
08	Transmit-Error Insertion Control
09–0A	Reserved
0C	BERT Status Register
0D	Reserved
0E	BERT Status Register Latched
10	BERT Status Register Interrupt Enable
11–13	Reserved
14	Receive Bit-Error Count Register 1
15	Receive Bit-Error Count Register 2
16	Receive Bit-Error Count Register 3
17	Receive Bit-Error Count Register 4
18	Receive Bit-Count Register 1
19	Receive Bit-Count Register 2
1A	Receive Bit-Count Register 3
1B	Receive Bit-Count Register 4
1C–1E	Reserved
1F	Set to 02h for access to BERT Register Bank

硬件考虑事项

不用改变PCB就可以用DS26303替换现有应用中的IDT82V2048。需要做的是根据目标应用改变外部器件值。图1为DS26303推荐的网络端接电路，表11为DS26303正确端接时需要的器件值。

发送器

IDT82V2048要求发送端电阻串联接入TTIP和TRING输出，建议这些电阻应该为0Ω (T1 3.3V模式)，9.5Ω (E1 75Ω同轴)或者9.1Ω (E1 120Ω双绞线)。DS26303不要求电阻，所以所有模式中的电阻都应该为0Ω。

接收器

在接收侧，IDT82V2048要求端接阻抗为12.4Ω (T1 3.3V模式)，9.31Ω (E1 75Ω同轴)或者15Ω (E1 120Ω双绞线)。当使用外部阻抗模式时，DS26303的所有情况都要求用15Ω端接电阻；当使用DS26303的软件选取阻抗匹配模式，不需要任何电阻。IDT82V2048要求使用1kΩ电阻同RTIP和RRING管脚串联。如果DS26303采用软件选取端接/阻抗匹配模式，这些1kΩ的电阻可以用0Ω电阻代替。


图1. LIU前端电路图

表11. LIU前端值

Mode	Component	75Ω Coaxial	120Ω Twisted Pair	100Ω/110Ω Twisted Pair
Tx Capacitance	Ct	560pF (typ). Adjust for board parasitics for optimal return loss.
Tx Protection	Dt	International Rectifier: 11DQ04 or 10BQ060 Motorola: MBR0540T1
Rx Transformer 1:2	TFr	Pulse: T1124 (0°C to +70°C)
Tx Transformer 1:2	TFt	Pulse: T1114 (-40°C to +85°C)
Tx Decoupling (ATVDD)	C1	Common decoupling for all eight channels is 68µF.
Tx Decoupling (ATVDD)	C2	Recommended decoupling per channel is 0.1µF.
Rx Decoupling (AVDDn)	C3	Common decoupling for all eight channels is 68µF.
Rx Decoupling (AVDDn)	C4	Common decoupling for all eight channels is 0.1µF.
Rx Termination	C5	When in external impedance mode, Rx capacitance for all eight channels is 0.1µF. Do not populate if using internal impedance mode.
Rx Termination	Rt	When in external impedance mode, the two resistors for all modes shall be 15.0Ω ±1%. Do not populate if using internal impedance mode.
Voltage Protection	TVS1	SGS-Thomson: SMLVT 3V3 (3.3V transient suppressor)