它们对应ARM手册中的名称为
ISER Interrupt Set-Enable Registers
ICER Interrupt Clear-Enable Registers
ISPR Interrupt Set-Pending Register
ICPR Interrupt Clear-Pending Register
IABR Active Bit Register
IPR Interrupt Priority Registers
每个寄存器有240位,以Interrupt Set-Enable Registers说明,ISER[0]对应中断源0~31,ISER[1]对应中断源32~63,STM32只有60个中断源,所以没有ISER[2:7]。
参考STM32技术参考手册中的中断向量表,中断源的位置为:
位置0 - WWDG Window Watchdog interrupt
位置1 - PVD PVD through EXTI Line detection interrupt
位置2 - TAMPER Tamper interrupt
位置58 - DMA2_Channel3 DMA2 Channel3 global interrupt
位置59 - DMA2_Channel4_5 DMA2 Channel4 and DMA2 Channel5 global interrupts
2)、系统控制寄存器组
STM32的固件库中有如下定义:
typedef struct
{
vuc32 CPUID;
vu32 ICSR;
vu32 VTOR;
vu32 AIRCR;
vu32 SCR;
vu32 CCR;
vu32 SHPR[3];
vu32 SHCSR;
vu32 CFSR;
vu32 HFSR;
vu32 DFSR;
vu32 MMFAR;
vu32 BFAR;
vu32 AFSR;
} SCB_TypeDef; /* System Control Block Structure */
它们对应ARM手册中的名称为
CPUID CPUID Base Register
ICSR Interrupt Control State Register
VTOR Vector Table Offset Register
AIRCR Application Interrupt/Reset Control Register
SCR System Control Register
CCR Configuration Control Register
SHPR System Handlers Priority Register
SHCSR System Handler Control and State Register
CFSR Configurable Fault Status Registers
HFSR Hard Fault Status Register
DFSR Debug Fault Status Register
MMFAR Mem Manage Address Register
BFAR Bus Fault Address Register
AFSR Auxiliary Fault Status Register
3)、系统时钟寄存器组
STM32的固件库中有如下定义:
typedef struct
{
vu32 CTRL;
vu32 LOAD;
vu32 VAL;
vuc32 CALIB;
} SysTick_TypeDef;
它们对应ARM手册中的名称为
CTRL SysTick Control and Status Register
LOAD SysTick Reload Value Register
VAL SysTick Current Value Register
CALIB SysTick Calibration Value Register
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